To handle the triple hidden terminal problems, this paper proposes OCO, an asynchronous multi-channel MAC protocol with opportunistic cooperation for wireless sensor networks. By adopting opportunistic cooperation, OC...
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The master/worker (MW) paradigm can be used to implement parallel discrete event simulations (PDES) on metacomputing systems. MW PDES applications incur overheads not found in conventional PDES executions executing on...
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ISBN:
(纸本)9780769537139
The master/worker (MW) paradigm can be used to implement parallel discrete event simulations (PDES) on metacomputing systems. MW PDES applications incur overheads not found in conventional PDES executions executing on tightly coupled machines. We introduce four techniques for reducing these overheads on public resource and desktop grid infrastructures Work unit caching, pipelined state updates, expedited message delivery, and adaptive work unit scheduling mechanisms are described that provide significant reduction in overall overhead when used in tandem. We present performance results showing that an optimized MW PDES system can exhibit performance comparable to a traditional PDES system for a queueing network and a particle physics simulation.
SystemC is a system-level modeling language and simulation framework which facilitates design and verification of processor designs at different levels. Recently, SystemC is becoming a popular choice for designers of ...
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ISBN:
(纸本)9780769537139
SystemC is a system-level modeling language and simulation framework which facilitates design and verification of processor designs at different levels. Recently, SystemC is becoming a popular choice for designers of both System-On-Chip (SoC) and embedded processors, clue to its adaptability at cycle as well as transaction levels, and ability to model concurrent processes. However, the single threaded simulation kernel inherent to SystemC, prevents it froth utilizing the potential computing power of symmetric multiprocessing (SMP) machines to speed up hardware simulation. We present a parallel SystemC simulation kernel, which is implemented using parallel programming techniques and leverages the parallel execution capabilities of multi-core machines to speed up hardware simulation. We discuss the mechanism we use for mapping parallel SystemC modules into different cores. Finally we report the performance of the parallelized SystemC kernel using a linear pipelined performance model and a pipelined performance model tailored to exhibit the behavior of real world simulation. Our results demonstrate that the performance improvement obtained by using parallelized SystemC for simulation of the above models is significant and improves with increasing design complexity of the simulated design and the number of cores in the machine running the simulators.
A methodology and its associated algorithms are presented for mapping a novel, field-based vehicular mobility model onto graphical processing unit computational platform for simulating mobility in large-scale road net...
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ISBN:
(纸本)9780769537139
A methodology and its associated algorithms are presented for mapping a novel, field-based vehicular mobility model onto graphical processing unit computational platform for simulating mobility in large-scale road networks. Of particular focus is the achievement of real-time execution, on desktop platforms, of vehicular mobility on road networks comprised of millions of nodes and links, and multi-million counts of simultaneously active vehicles. The methodology is realized in a system called GARFIELD, whose implementation details and performance study are described The runtime characteristics of a prototype implementation are presented that show real-time performance in simulations of networks at the scale of a few states of the US road networks.
In this paper we propose a scalable admission control scheme for the QoS sensitivity traffic in core-stateless networks. In our scheme, the ingress routers perform admissibility test in a fully distributed and paralle...
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ISBN:
(纸本)9780769535579
In this paper we propose a scalable admission control scheme for the QoS sensitivity traffic in core-stateless networks. In our scheme, the ingress routers perform admissibility test in a fully distributed and parallel fashion for requests by dint of our bandwidth dividing based virtual link mechanism. Then, we introduce a novel two phase token passing mechanism to adaptively optimize the proportion of bandwidth dividing among contending edge routers according to the dynamic of their traffic. In addition, we adopt a measurement based admission decision-making criterion to gain the benefit of high utilization of statistical multiplexing. Our simulation results are very promising indicating that even under very high request load it is possible to perform admission control and resource allocation in parallel without suffering in terms of response time, packet loss rate, or utilization.
A parallel computer architecture and a distributed software platform for automation and control of general anesthesia is proposed in this paper The system is a prototype research platform, intended to help on the deve...
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ISBN:
(纸本)9780769536804
A parallel computer architecture and a distributed software platform for automation and control of general anesthesia is proposed in this paper The system is a prototype research platform, intended to help on the development, simulation and test of new control algorithms for general anesthesia. It must be safe when used in real tests and flexible enough to allow the integration of new software modules. The system is composed by two computers, with the specific tasks of anesthesia control and process supervision. The platform makes use of TANGO, a specialized framework for distributed control systems, which provides software mechanisms useful to fulfill the project requirements. The architecture and the set of mechanisms proposed in this paper provide a high degree of flexibility to research on control algorithms, while ensuring the safeness of the whole procedure.
The proceedings contain 18 papers. The topics discussed include: an approach for validation of semantic composability in simulation models;symbiotic simulation model validation for radiation detection applications;cau...
ISBN:
(纸本)9780769537139
The proceedings contain 18 papers. The topics discussed include: an approach for validation of semantic composability in simulation models;symbiotic simulation model validation for radiation detection applications;causal program slicing;a performance evaluation of the lightweight time warp protocol in optimistic parallelsimulation of DEVS-based environmental model;scalable time warp on blue gene supercomputers;real-time security exercises on a realistic interdomain routing experiment platform;modeling and evaluation of rescue operations using mobile communication devices;parallelizing SystemC kernel for fast hardware simulation on SMP machines;GPU-based real-time execution of vehicular mobility models in large-scale road network scenarios;an efficient and adaptive mechanism for parallelsimulation replication;and using REST web-services architecture for distributedsimulation.
Metadata service system is a latent access bottleneck in a large distributed storage system. The traditional methods of metadata distribution and management does not take more dynamic load balancing into account espec...
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ISBN:
(纸本)9780819473592
Metadata service system is a latent access bottleneck in a large distributed storage system. The traditional methods of metadata distribution and management does not take more dynamic load balancing into account especially in heterogeneous MDS(MetaData Server, MDS) cluster, therefore it is very easy to become hotspots. This paper introduces a linear chain load balancing policy based on hybrid method which has both the advantages of the directory subtree partitioning and the pure hashing in MDS cluster. Comparing with traditional methods, it can dynamically distributes and manages metadata according to the workload of every MDS in heterogeneous MDS cluster. Finally it is proved to have good load balancing by analyzing the arithmetic theoretically and simulation test.
The proceedings contain 12 papers. The topics discussed include: characterizing fault tolerance in genetic programming;proactive information caching for efficient resource discovery in a self-structured grid;crystal-g...
ISBN:
(纸本)9781605585840
The proceedings contain 12 papers. The topics discussed include: characterizing fault tolerance in genetic programming;proactive information caching for efficient resource discovery in a self-structured grid;crystal-growth-inspired algorithms for computational grids;an innovative perspective on mapping in grids;a distributed ant-based algorithm for numerical optimization;evolutionary P2P network adaptively changing its topologies for reliable searching;an evaporative approach to handle dynamics in diffusive aggregation schemes;asynchronous simulation of a self-synchronized duty-cycling mechanism for mobile sensor networks;power-efficient epidemic information dissemination in sensor networks;swarm intelligence based energy saving and load balancing in wireless ad hoc networks;high performance genetic programming on GPU;and fastest parallel molecular algorithms for the elliptic curve discrete logarithm problem over GF(2n).
SRAM (static random access memory)-based pipelined algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high-throughput IP lookup. Multiple pipelines can be ut...
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SRAM (static random access memory)-based pipelined algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high-throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines, as well as across different stages of each pipeline, must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order (i.e. the sequence) must be preserved. In this paper, we propose a parallel SRAM-based multi-pipeline architecture for IP lookup. A two-level mapping scheme is developed to balance the memory requirement among the pipelines as well as across the stages in each pipeline. To balance the traffic, we propose an early caching scheme to exploit the data locality inherent in the architecture. Our technique uses neither a large reorder buffer nor complex reorder logic. Instead, a flow-aware queuing scheme exploiting the flow information is used to maintain the intra-flow sequence. Extensive simulation using real-life traffic traces shows that the proposed architecture with 8 pipelines can achieve a throughput of up to 10 billion packets per second, i.e. 3.2 Tbps for minimum size (40 bytes) packets, while preserving intra-flow packet order. (c) 2009 Elsevier Inc. All rights reserved.
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