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Provably efficient scheduling for languages with fine-grained parallelism 95

Provably efficient scheduling for languages with fine-graine...

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Blelloch, Guy E. Gibbons, Phillip B. Matias, Yossi Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897917179

Most high-level parallel programming languages allow for fine-grained parallelism. Programs written in such languages can express the full parallelism in the program without specifying the mapping of program tasks to processors. When executing such programs, the major concern is to dynamically schedule tasks to processors in order to minimize execution time and the amount of memory needed. In this paper, a class of parallel schedules that are provably efficient in both time and space, even for programs whose task structure is revealed only during execution are identified. Following this, an efficient dynamic scheduling algorithm that generates schedules in this class, for languages with nested fine-grained parallelism is described.

关键词： parallel processing systems

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Efficient techniques for fast nested barrier synchronization 95

Efficient techniques for fast nested barrier synchronization

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Ramakrishnan, Vara Scherson, Isaac D. Subramanian, Raghu Univ of California Irvine CA United States

ISBN: (纸本)9780897917179

Two hardware barrier synchronization schemes are presented which can support deep levels of control nesting in data parallel programs. Hardware barriers are usually an order of magnitude faster than software implementations. Since large data parallel programs often have several levels of nested barriers, these schemes provide significant speedups in the execution of such programs on MIMD computers. The first scheme performs code transformations and uses two single-bit-trees to implement unlimited levels of nested barriers. However, this scheme increases the code size. The second scheme uses a more expensive integer-tree to support an exponential number of nested barriers without increasing the code size. Using hardware already available on commercial MIMD computers, this scheme can support more than four billion levels of nesting.

关键词： parallel processing systems

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Randomized parallel 3D convex hull algorithm for coarse grained multicomputers

Randomized parallel 3D convex hull algorithm for coarse grai...

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proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Dehne, Frank Deng, Xiaotie Dymond, Patrick Fabri, Andreas Khokhar, Ashfaq A. Carleton Univ Ottawa Canada

We present a randomized parallel algorithm for constructing the 3D convex hull on a generic p-processor coarse grained multicomputer with arbitrary interconnection network and n/p local memory per processor, where n/p ≥ p2+Ε (for some arbitrarily small Ε > 0). For any given set of n points in 3-space, the algorithm computes the 3D convex hull, with high probability, in O(n log n÷p) local computation time and O(1) communication phases with at most O(n÷p) data sent/received by each processor. That is, with high probability, the algorithm computes the 3D convex hull of an arbitrary point set in time O(n log n÷p + Γn,p), where Γn,p denotes the time complexity of one communication phase. In the terminology of the BSP model, our algorithm requires, with high probability, O(1) supersteps and a synchronization period Θ(n log n÷p). In the LogP model, the execution time of our algorithm is asymptotically optimal for several architectures.

关键词： parallel algorithms

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parallel algorithms for the circuit value update problem 95

Parallel algorithms for the circuit value update problem

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Leiserson, Charles E. Randall, Keith H. MIT Lab for Computer Science Cambridge MA United States

ISBN: (纸本)9780897917179

The circuit value update problem is the problem of updating values in a representation of a combinational circuit when some of the inputs are changed. We assume for simplicity that each combinatorial element has bounded fan-in and fan-out and can be evaluated in constant time. This problem is easily solved on an ordinary serial computer in O(W + D) time, where W is the number of elements in the altered subcircuit and D is the subcircuit's embedded depth (its depth measured in the original circuit). In this paper, we show how to solve the circuit value update problem efficiently on a P-processor parallel computer. We give a straightforward synchronous, parallel algorithm that runs in O(W/P + D lg P) expected time. Our main contribution, however, is an optimistic, asynchronous, parallel algorithm that runs in O(W/P + D + lg W + lg P) expected time, where W and D are the size and embedded depth, respectively, of the 'volatile' subcircuit, the subcircuit of elements that have inputs which either change or glitch as a result of the update. To our knowledge, our analysis provides the first analytical bounds on the running time of an optimistic algorithm.

关键词： parallel algorithms

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Optimal trade-offs between size and slowdown for universal parallel networks

Optimal trade-offs between size and slowdown for universal p...

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Meyer auf der Heide, Friedhelm Storch, Martin Wanka, Rolf Univ of Paderborn Paderborn Germany

In this paper, we address the question how efficiently a single constant-degree processor network can simulate the computation of any constant-degree processor network. We show the following lower bound trade-off: If M is an arbitrary constant-degree processor network of size m that can simulate all constant-degree processor networks of size n with slowdown s, then m·s = Ω(n log m). Our trade-off holds for a very general model of simulations. It covers all previously considered models and all known techniques for simulations among networks. For m ≥ n, this improves a previous lower bound by a factor of log log n, proved for a weaker simulation model. For m < n, this is the first non-trivial lower bound for this problem. In this case, this lower bound is asymptotically tight.

关键词： parallel processing systems

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parallel sorting with limited bandwidth 95

Parallel sorting with limited bandwidth

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proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Adler, Micah Byers, John W. UC Berkeley Berkeley CA United States

ISBN: (纸本)9780897917179

We study the problem of sorting on a parallel computer with limited communication bandwidth. By using the recently proposed PRAM(m) model, where p processors communicate through a small, globally shared memory consisting of m bits, we focus on the trade-off between the amount of local computation and the amount of inter-processor communication required for parallel sorting algorithms. We prove a lower bound of Ω(n log m/m) on the time to sort n numbers in an exclusive-read variant of the PRAM (m) model. We show that Leighton's Columnsort can be used to give an asymptotically matching upper bound in the case where m grows as a fractional power of n. The bounds are of a surprising form, in that they have little dependence on the parameter p. This implies that attempting to distribute the workload across more processors while holding the problem size and the size of the shared memory fixed will not improve the optimal running time of sorting in this model. We also show that both the upper and the lower bound can be adapted to bridging models that address the issue of limited communication bandwidth: the LogP model and the BSP model. The lower bounds provide convincing evidence that efficient parallel algorithms for sorting rely strongly on high communication bandwidth.

关键词： parallel processing systems

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Modeling the benefits of mixed data and task parallelism 95

Modeling the benefits of mixed data and task parallelism

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Chakrabarti, Soumen Demmel, James Yelick, Katherine U.C. Berkeley Berkeley CA United States

ISBN: (纸本)9780897917179

Mixed task and data parallelism exists naturally in many applications, but utilizing it may require sophisticated scheduling algorithms and software support. Recently, significant research effort has been applied to exploiting mixed parallelism in both theory and systems communities. In this paper, we ask how much mixed parallelism will improve performance in practice, and how architectural evolution impacts these estimates. First, we build and validate a performance model for a class of mixed task and data parallel problems based on machine and problem parameters. Second, we use this model to estimate the gains from mixed parallelism for some scientific applications on current machines. This quantifies our intuition that mixed parallelism is best when either communication is slow or the number of processors is large. Third, we show that, for balanced divide and conquer trees, a simple one-time switch between data and task parallelism gets most of the benefit of general mixed parallelism. Fourth, we establish upper bounds to the benefits of mixed parallelism for irregular task graphs. Apart from these detailed analyses, we provide a framework in which other applications and machines can be evaluated.

关键词： parallel processing systems

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Efficient message passing interface (MPI) for parallel computing on clusters of workstations 95

Efficient message passing interface (MPI) for parallel compu...

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proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Bruck, Jehoshua Dolev, Danny Ho, Ching-Tien Rosu, Marcel-Catalin Strong, Ray California Inst of Technology Pasadena CA United States

ISBN: (纸本)9780897917179

An efficient design and implementation of the collective communication part in a Message Passing Interface (MPI) that is optimized for clusters of workstations is described. The system which consist of two main components, the MPI-CCL layer and a User-level Reliable Transport Protocol (URTP), is integrated with the operating system via an efficient kernel extension mechanism. The system is then implemented on a collection of IBM RS/6000 workstations connected via a 10Mbit Ethernet LAN. Results indicate that the performance of the MPI Broadcast (on top of Ethernet) is about twice as fast as a recently published software implementation of broadcast on top of ATM.

关键词： parallel processing systems

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On testing consecutive-ones property in parallel 95

On testing consecutive-ones property in parallel

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Annexstein, F.S. Swaminathan, R.P. Univ of Cincinnati Cincinnati OH United States

ISBN: (纸本)9780897917179

A n × m (0,1)-matrix is said to satisfy the consecutive-ones property if there is a permutation of the rows of the matrix such that in each column all non-zero entries are adjacent. The problem of determining such a permutation, if one exists, is the consecutive-ones property problem. Previously, Klein and Reif [13] gave a parallel solution for the consecutive-ones property problem with an algorithm based on complicated parallel PQ-tree manipulations. The work complexity of this algorithm was improved in [14] to run in time O(log2 n) with a linear number of CRCW processors. We present a new algorithm for this problem, based on a less sophisticated data structure, that improves upon the processor bounds of the previous algorithms by a factor of log n/log log n is general, and by a factor of log n for sufficiently dense problem instances. Our algorithm uses a novel divide-and-conquer approach, and uses for a fundamental data structure the decomposition of graphs into tri-connected components. Solutions to the consecutive-ones problem have important applications to a variety of problems in computational molecular biology, databases, distributed computing, VLSI placement and routing, and graph and network theory.

关键词： parallel processing systems

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Lower bounds for randomized exclusive write PRAMs 95

Lower bounds for randomized exclusive write PRAMs

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： MacKenzie, Philip D. Sandia Natl Lab Albuquerque NM United States

ISBN: (纸本)9780897917179

In this paper we study the question: How useful is randomization in speeding up Exclusive Write PRAM computations? Our results give further evidence that randomization is of limited use in these types of computations. First we examine a compaction problem on both the CREW and EREW PRAM models, and we present randomized lower bounds which match the best deterministic lower bounds known. (For the CREW PRAM model, the lower bound is asymptotically optimal). These are the first non-trivial randomized lower bounds known for the compaction problem on these models. We show that our lower bounds also apply to the problem of approximate compaction. Next we examine the problem of computing boolean functions on the CREW PRAM model, and we present a randomized lower bound which improves on the previous best randomized lower bound for many boolean functions, including the OR function. (The previous lower bounds for these functions were asymptotically optimal, but we improve the constant multiplicative factor). We also give an alternate proof for the randomized lower bound on PARITY, which was already optimal to within a constant additive factor. Lastly, we give a randomized lower bound for integer merging on an EREW PRAM which matches the best deterministic lower bound known. In all our proofs, we use the Random Adversary method, which has previously only been used for proving lower bounds on models with Concurrent Write capabilities. Thus this paper also serves to illustrate the power and generality of this method for proving parallel randomized lower bounds.

关键词： parallel processing systems

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