The implementation of a distributed digital logic simulation algorithm on a network of workstations is presented. The simulation of digital circuits is done using a demand driven approach. The simulation is performed ...
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We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by ...
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We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.
Most experimental studies of the performance of parallelsimulation protocols use speedup or number of events processed per unit time as the performance metric. Although helpful in evaluating the usefulness of paralle...
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Most experimental studies of the performance of parallelsimulation protocols use speedup or number of events processed per unit time as the performance metric. Although helpful in evaluating the usefulness of parallelsimulation for a given simulation model, these metrics tell us little about the efficiency of the simulation protocol used. In this paper, we describe an Ideal simulation Protocol (ISP), based on the concept of critical path, which experimentally computes the best possible execution time for a simulation model on a given parallel architecture. Since ISP computes the bound by actually executing the model on the given parallel architecture, it is much more realistic than that computed by a uniprocessor critical path analysis. The paper illustrates, using parameterized synthetic benchmarks, how an ISP-based performance evaluation can lead to much better insights into the performance of parallelsimulation protocols than what would be gained from speedup graphs alone.
A new conservative algorithm for both parallel and sequential simulation of networks is described. The technique is motivated by the construction of a high performance simulator for ATM networks. It permits very fast ...
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A new conservative algorithm for both parallel and sequential simulation of networks is described. The technique is motivated by the construction of a high performance simulator for ATM networks. It permits very fast execution of models of ATM systems, both sequentially and in parallel. A simple analysis of the performance of the system is made. Initial performance results from parallel and sequential implementations are presented and compared with comparable results from an optimistic TimeWarp based simulator. It is shown that the conservative simulator performs well when the 'density' of messages in the simulated system is high, a condition which is likely to hold in many interesting ATM scenarios.
parallel independent replicated simulation (PIRS) is an effective approach to speed up the simulation processes. In a PIRS, a single simulation run is executed by multiple computers in parallel. The statistical proper...
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ISBN:
(纸本)1565550277
parallel independent replicated simulation (PIRS) is an effective approach to speed up the simulation processes. In a PIRS, a single simulation run is executed by multiple computers in parallel. The statistical properties for a PIRS may be affected by the scheduling policies. For an unbiased PIRS scheduling policy, a reliable distributed computing environment is required. We consider an unbiased PIRS scheduling policy on a distributed platform such as a network of workstations. We observe that including more computing resources may degrade the performance of PIRS. Simple rules are proposed to select processors for PIRS.
Data Distribution Management (DDM) is a High Level Architecture/Run-time Infrastructure (HLA/RTI) service that manages the distribution of state updates and interaction information in large scale distributed simulatio...
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ISBN:
(纸本)0769513484
Data Distribution Management (DDM) is a High Level Architecture/Run-time Infrastructure (HLA/RTI) service that manages the distribution of state updates and interaction information in large scale distributedsimulations, limits and controls the volume of data exchanged during the simulation. In this paper we focus upon the following three DDM schemes: Region-Based, Fixed and Dynamic Grid-Based techniques. In an effort to determine the most efficient model for applying the DDM service, we developed a mini-RTY Kit framework and propose a set of benchmarks to compare these DDM schemes. Using the RTI Kit, we performed extensive simulation experiments and present our analysis of the results of numerous federation executions.
In optimistic simulations, checkpointing techniques are often used to reduce the overhead caused by state saving. In this paper, we propose event reconstruction as a technique with which to reduce the overhead caused ...
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ISBN:
(纸本)0769521118
In optimistic simulations, checkpointing techniques are often used to reduce the overhead caused by state saving. In this paper, we propose event reconstruction as a technique with which to reduce the overhead caused by event saving, and compare its memory consumption and execution time to the results obtained by dynamic checkpointing. As the name implies, event reconstruction reconstructs input events and anti-events from the differences between adjacent states, and does not save input events in the event queue. For simulations with fine event granularity and small state size, such as the logic simulation of VLSI circuitry, event reconstruction can yield an improvement in execution time as well as a significant reduction in memory utilization when compared to dynamic checkpointing. Moreover, this technique facilitates load migration because only the state queue needs to be moved from one processor to another.
In earlier work cloning is proposed as a means for efficiently splitting a running simulation midway through its execution into multiple parallelsimulations. In simulation cloning, clones usually are able to share co...
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ISBN:
(纸本)0769523838
In earlier work cloning is proposed as a means for efficiently splitting a running simulation midway through its execution into multiple parallelsimulations. In simulation cloning, clones usually are able to share computations that occur early in the simulation, but as their states diverge individual LPs are replicated as necessary so that their computations proceed independently. However if overtime the state of the clones (or their constituent LPs) converges there is, as of yet, no means for recombining them. In this case some efficiency is lost because they will execute identical events. This idea is the reverse of cloning, as we merge logical processes that have been previously cloned and we show that this can further increase efficiency because the new uncloned LPs will complete computations that would otherwise be duplicated. We discuss our implementation of merging, and illustrate its effectiveness in several example simulation scenarios.
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