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Experience in massively parallel discrete event simulation 93

Experience in massively parallel discrete event simulation

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proceedings of the 5th annual acm symposium on parallel algorithms and architectures

作者： Greenberg, Albert G. Lubachevsky, Boris D. Wang, Li-Chung AT and T Bell Laboratories United States University of Texas Austin United States

ISBN: (纸本)0897915992

Discrete event simulation of complex systems is one of the most important problems in scientific and industrial computing. It is not uncommon for a single simulation run to take hours on a high speed workstation. Massively parallel computers provide opportunities for simulating complex systems significantly faster. At the heart of the computational difficulties in parallel simulation are (i) random, data-dependent events that couple subsystems, and (ii) asymmetries wherein some subsystems receive a disproportionate number of events, leading to severe load imbalances. In this paper, we discuss a parallel simulation of a complex system-a large asymmetric circuit-switched network, with state-dependent control-and methods we have apphed to overcome both types of difficulties just mentioned. In a worst case sense, we show that the problem is hard: In particular, simulation of a network with just three nodes is P-complete. However, we show that a general purpose synchronous relaxation method uncovers the parallelism inherent in practical, realistic cases. In addition, we show that special purpose (specific to circuit-switched simulations) parallel methods allow us to profitably assign more processors to subsystems receiving more events, and thereby handle load imbalances. Promising performance results are reported for a 16384 processor MasPar MP-1 implementation, on a realistic 114 node network simulation scenario. © 1993 acm.

关键词： Discrete event simulation

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Brief announcement: RedRem: A parallel redundancy remover 11

Brief announcement: RedRem: A parallel redundancy remover

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proceedings of the twenty-third annual acm symposium on parallelism in algorithms and architectures

作者： Acharya, Hrishikesh Gouda, Mohamed University of Texas at Austin Austin TX United States National Science Foundation Washington DC United States

ISBN: (纸本)9781450307437

Policies defined by a sequence of predicate-decision rules, with first-match semantics, are widely used;a notable example is their use in firewalls, where the rules are used to decide whether to accept or discard each packet. Owing to the critical importance of correctness of such policies, as well as the need for high performance, they have been the subject of considerable analysis. In earlier work, we have demonstrated that the problem of removing redundant rules from firewalls is theoretically equivalent to verifying that a firewall satisfies a property, and proposed that this theorem be used to build a high performance redundancy remover. In this paper, we realize this promise, and build a fast linear-space redundancy remover, one to three orders of magnitude faster than current approaches. Further, we show that our algorithm is easy to parallelize- there exists a natural way to partition a large instance of the problem into independent small ones. © 2011 Authors.

关键词： Redundancy

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Optimal VLSI architectures for multidimensional DFT 89

Optimal VLSI architectures for multidimensional DFT

引用

1st annual acm symposium on parallel algorithms and architectures, SPAA 1989

作者： Bilardi, Gianfranco Hornick, Scot W. Sarrafzadeh, Majid Department of Computer Science Cornell University Upson Hall IthacaNY14853 United States Andersen Consulting Center for Strategic Tech. Res. 100 S. Wacker ChicagoIL60606 United States Dept. of Elec. Eng. and Comp. Sci. Technological Institute Northwestern University EvanstonIL60208 United States

ISBN: (纸本)089791323X

A family of VLSI architectures for computing an (n 1 × n 2 × • • " × nd)-point multidimensional D1VF (MDDFT) over Zm, the ring of integers modulo M, is presented. These architectures achieve VLSI area A = 0 ((NZlog2M)/T 2) for any comptitation time T ϵ [ω(logN),O (ωNlogM)], where N = I'Int and it is k=l assumed that logM = O(logN). A lower bound argument is developed to show that the proposed architectures are area-Time optimal. The appficability of these architectures to computation of the MDDFT over the complex field is also discussed. Using fixed-point arithmetic with b bits of precision, their area-Time performance is AT2= O(N2b 2) for any computation time T ϵ [ω(logN),O(√Nb)]. © 1989 acm.

关键词： Fixed point arithmetic

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Field-Split parallel Architecture for High Performance Multi-Match Packet Classification Using FPGAs 09

Field-Split Parallel Architecture for High Performance Multi...

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21st acm symposium on parallelism in algorithms and architectures

作者： Jiang, Weirong Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781605586069

Multi-match packet classification is a critical function in network intrusion detection systems (NIDS), where all matching rules for a packet need to be reported. Most of the previous work is based on ternary content addressable memories (TCAMs) which are expensive and are not scalable with respect to clock rate, power consumption, and circuit area. This paper studies the characteristics of real-life Snort NIDS rule sets, and proposes a novel SRAM-based architecture. The proposed architecture is called field-split parallel bit vector (FSBV) where some header fields of a packet are further split into bit-level subfields. Unlike previous multi-match packet classification algorithms which suffer from memory explosion, the memory requirement of FSBV is linear in the number of rules. FPGA technology is exploited to provide high throughput and to support dynamic updates. Implementation results show that our architecture can store on a single Xilinx Virtex-5 FPGA the full set of packet header rules extracted from the latest Snort NIDS and sustains 100 Gbps throughput for minimum size (40 bytes) packets. The design achieves 1.25x improvement in throughput while the power consumption is approximately one fourth that of the state-of-the-art solutions.

关键词： FPGA multi-match packet classification NIDS SRAM

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Brief Announcement: Work Stealing through Partial Asynchronous Delegation 24

Brief Announcement: Work Stealing through Partial Asynchrono...

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36th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Wang, Jiawei Liu, Yutao Fu, Ming Haertig, Hermann Chen, Haibo Tech Univ Dresden Huawei Dresden Res Ctr Dresden Germany Huawei Dresden Res Ctr Dresden Germany Huawei Cent Software Inst Shenzhen Peoples R China Tech Univ Dresden Dresden Germany Shanghai Jiao Tong Univ Huawei Cent Software Inst Shanghai Peoples R China

ISBN: (纸本)9798400704161

Work stealing is a well-established technique in multi-core systems that aims to improve load balancing and task scheduling efficiency. Each processing unit maintains its own task queue, and when idle, it steals tasks from other units. Traditional work-stealing approaches face performance bottlenecks due to costly synchronization primitives and contention arising from concurrent access by both the queue owner and thieves. The state-of-the-art solution addresses these issues through coarse-grained synchronization;however, it restricts stealing in specific scenarios, thereby limiting parallelism. We introduce PadWS, a partial and asynchronous delegated work-stealing algorithm. PadWS employs a block-based design in which, under common cases, the queue owner and thieves work on separate blocks, reducing metadata contention. Delegation is partially enabled for the block in which the owner is located, allowing thieves to steal from it-an approach that deviates from the current block-based approach. Additionally, our delegation strategy is asynchronous, which removes the need for thieves to spin-wait after sending a request.

关键词： parallel processing scheduling work stealing delegation

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Optimal parallel two dimensional pattern matching 93

Optimal parallel two dimensional pattern matching

引用

5th annual acm symposium on parallel algorithms and architectures, SPAA 1993

作者： Amir, Amihood Benson, Gary Farach, Martin Georgia Tech United States Department of Mathematics University of Southern California DRB 155 1024 W 36th PI Los AngelesCA90089-1113 United States DIMACS United States College of Computing Georgia Institute of Technology AtlantaGA30332-0280 United States

ISBN: (纸本)0897915992

We present a parallel algorithm for two dimensional matching. This algorithm is optimal in two ways. First, the total number of operations on the text is linear. Second, the algorithm takes time O(logm) on a CREW PRAM, thus matching the lower bound for string matching on a PRAM without concurrent writes. On a CRCW, the algorithm runs in time O(loglogro). Finding such an algorithm was a problem posed in 1985 and has been open since. © 1993 acm.

关键词： parallel algorithms

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Locating faults in a constant number of parallel testing rounds 89

Locating faults in a constant number of parallel testing rou...

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1st annual acm symposium on parallel algorithms and architectures, SPAA 1989

作者： Beigel, Richard Kosaraju, S. Rao Sullivan, Gregory F. Dept. of Computer Science Johns Hopkins University BaltimoreMD21218 United States

ISBN: (纸本)089791323X

Consider a system of processing elements in which elements may administer tests to other elements. We show, surprisingly, that a constant, number of rounds of parallel testing are sufficient to identify all faults (in all cases where fault identification is possible). We also present an O(loglogn/t t) algorithm with a small constant of proportionality, where n denotes the total number of processors and t denotes the number of faulty processors. Both of these results improve upon the previous best, which was O(log n/t t) rounds. For the problems of identifying a single faulty processor (diagnosis-with-repair) and identifying a single good processor, we present an oblivious constant-Time algorithm using a fixed 3-regular interconnect that tolerates a linear number of faults. This contrasts with the well-known result that every oblivious algorithm for complete diagnosis must use a number of rounds that is linear in t. © 1989 acm.

关键词： parallel algorithms

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On testing consecutive-ones property in parallel 95

On testing consecutive-ones property in parallel

引用

proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Annexstein, F.S. Swaminathan, R.P. Univ of Cincinnati Cincinnati OH United States

ISBN: (纸本)9780897917179

A n × m (0,1)-matrix is said to satisfy the consecutive-ones property if there is a permutation of the rows of the matrix such that in each column all non-zero entries are adjacent. The problem of determining such a permutation, if one exists, is the consecutive-ones property problem. Previously, Klein and Reif [13] gave a parallel solution for the consecutive-ones property problem with an algorithm based on complicated parallel PQ-tree manipulations. The work complexity of this algorithm was improved in [14] to run in time O(log2 n) with a linear number of CRCW processors. We present a new algorithm for this problem, based on a less sophisticated data structure, that improves upon the processor bounds of the previous algorithms by a factor of log n/log log n is general, and by a factor of log n for sufficiently dense problem instances. Our algorithm uses a novel divide-and-conquer approach, and uses for a fundamental data structure the decomposition of graphs into tri-connected components. Solutions to the consecutive-ones problem have important applications to a variety of problems in computational molecular biology, databases, distributed computing, VLSI placement and routing, and graph and network theory.

关键词： parallel processing systems

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Fine-grain multithreading with the EM-X multiprocessor 97

Fine-grain multithreading with the EM-X multiprocessor

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Sohn, Andrew Kodama, Yuetsu Ku, Jui Sato, Mitsuhisa Sakane, Hirofumi Yamana, Hayato Sakai, Shuichi Yamaguchi, Yoshinori New Jersey Inst of Technology Newark NJ United States

ISBN: (纸本)9780897918909

Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multiprocessor through empirical studies. The EM-X provides hardware supports for fine-grain multithreading, including a by-passing mechanism for direct remote reads and writes, hardware FIFO thread scheduling, and dedicated instructions for generating fixed-sized communication packets. Bitonic sorting and Fast Fourier Transform are selected for experiments. Parameters that characterize the performance of multithreading are investigated, including the number of threads, the number of thread switches, the run length, and the number of remote reads. Experimental results indicate that the best communication performance occurs when the number of threads is two to four. FFT yielded over 95% overlapping due to a large amount of computation and communication parallelism across threads. Even in the absence of thread computation parallelism, multithreading helps overlap over 35% of the communication time for bitonic sorting.

关键词： parallel processing systems

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Efficient compilation of high-level data parallel algorithms 94

Efficient compilation of high-level data parallel algorithms

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proceedings of the 6th annual acm symposium on parallel algorithms and architectures

作者： Suciu, Dan Tannen, Val Univ. of Pennsylvania Philadelpia

ISBN: (纸本)9780897916714

We present a high-level parallel calculus for nested sequences, NSC, offered as a possible theoretical “core” of an entire class of collection-oriented parallel languages. NSC is based on while-loops as opposed to general recursion. A formal, machine independent definition of the parallel time complexity and the work complexity of programs in NSC is given. Our main results are: (1) We give a translation method for a particular form of recursion, called map-recursion, into NSC, that preserves the time complexity and adds an arbitrarily small overhead to the work complexity, and (2) We give a compilation method for NSC into a very simple vector parallel machine, which preserves the time complexity and again adds an arbitrarily small overhead to the work complexity.

关键词： Calculations

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