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Elimination forest guided 2D sparse LU factorization 98

Elimination forest guided 2D sparse LU factorization

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proceedings of the 1998 10th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Shen, K. Jiao, X. Yang, T. Univ of California Santa Barbara CA United States

ISBN: (纸本)9780897919890

Sparse LU factorization with partial pivoting is important for many scientific applications and delivering high performance for this problem is difficult on distributed memory machines. Our previous work has developed an approach called S* that incorporates static symbolic factorization, supernode partitioning and graph scheduling. This paper studies the properties of elimination forests and uses them to guide supernode partitioning/amalgamation and execution scheduling. The new design with 2D mapping effectively identifies dense structures without introducing too many zeros in the BLAS computation and exploits asynchronous parallelism with low buffer space cost. The implementation of this code, called S+, uses supernodal matrix multiplication which retains the BLAS-3 level efficiency and avoids unnecessary arithmetic operations. The experiments show that S+ improves our previous code substantially and can achieve up to 11.04GFLOPS on 128 Cray T3E 450 MHz nodes, which is the highest performance reported in the literature.

关键词： parallel algorithms

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Proximity-Aware Directory-based Coherence for Multi-core Processor architectures 07

Proximity-Aware Directory-based Coherence for Multi-core Pro...

引用

19th annual symposium on parallelism in algorithms and architectures

作者： Brown, Jeffery A. Kumar, Rakesh Tullsen, Dean Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)9781595936677

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. This is exacerbated by the fact that interconnection speeds are not scaling well with technology. This paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores. These techniques exploit the differences in geometry between chip multiprocessors and traditional multiprocessor architectures. Directory-based protocols have been proposed as a scalable alternative to snoop-based protocols. In this paper, we discuss implementations of coherence for CMPs and propose and evaluate a novel directory-based coherence scheme to improve the performance of parallel programs on such processors. Proximity-aware coherence accelerates read and write misses by initiating cache-to-cache transfers from the spatially closest sharer. This has the dual benefit of eliminating unnecessary accesses to off-Chip memory, and minimizing the distance over which communicated data moves across the network. The proposed schemes result in speedups up to 74.9% for our workloads.

关键词： Chip Multiprocessors Coherence

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In-place techniques for parallel convex hull algorithms 3

In-place techniques for parallel convex hull algorithms

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3rd annual acm symposium on parallel algorithms and architectures, SPAA 1991

作者： Ghouse, Mujtaba R. Goodrich, Michael T. Dept. of Computer Science Johns Hopkins University BaltimoreMD21218-2686 United States

ISBN: (纸本)0897914384

We present a number of efficient parallel algorithms for constructing 2- and 3-dimensional convex hulls on a randomized CRCW PRAM. Specifically, we show how to build the convex hull of n pre-sorted points in the plane almost surely in O(1) time using O(n log n) processors, or, alternately, almost surely in O (log∗ n) time using an optimal number of processors. We also show how to find the convex hull of n unsorted points in R2 (resp., R3) in O(log2 n) time using O(n log h) work (resp., O(log2n) time using O(min{nlog2 h, n log n}) work), with very high probability, where h is the number of edges in the convex hull (h is O(n), but can be as small as O(l)). Our algorithms for unsorted input depend on the use of new in-place procedures, that is, procedures that are defined on a subset of elements in the input and that work without re-ordering the input. For the pre-sorted case we also exploit a technique that allows one to modify an algorithm that assumes it is given points so that it can be used on hulls;we call such algorithms point-hull invariant. © 1991 acm.

关键词： parallel algorithms

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Constructing trees in parallel 89

Constructing trees in parallel

引用

1st annual acm symposium on parallel algorithms and architectures, SPAA 1989

作者： Atallah, M.J. Kosaraju, S.R. Larmore, L.L. Miller, G.L. Teng, S.-H. Department of Computer Science Purdue University United States Department of Computer Science Johns Hopkins University United States ICS UC Irvine United States School of Computer Science CMU United States Department of Computer Science USC United States

ISBN: (纸本)089791323X

An O(log 2 n) time, n2/logn processor as well as an O(log n) time, n3/log n processor CREW deterministic parallel algorithms are presented for constructing Huffman codes from a given list of frequences. The time can be reduced to O(log n(loglog n) 2) on an CRCW model, using only n2/(log log n) 2 processors. Also presented is an optimal O(log n) time, O(n/log n) processor EREW parallel algorithm for constructing a tree given a list of leaf depths when the depths are monotonic. An O(log 2 n) time, n processor parallel algorithm is given for the general tree construction problem. We also give an O(log 2 n) time n2/log2n processor algorithm which finds a nearly optimal binary search tree. An O(log 2 n) time n 2 36 processor algorithm for recognizing linear context free languages is given. A crucial ingredient in achieving those bounds is a formulation of these problems as multiplications of special matrices which we call concave matrices. The structure of these matrices makes their parallel multiplication dramatically more efficient than that of arbitrary matrices. © 1989 acm.

关键词： parallel algorithms

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Scheduling Irregular parallel Computations on Hierarchical Caches 11

Scheduling Irregular Parallel Computations on Hierarchical C...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Fineman, Jeremy T. Gibbons, Phillip B. Simhadri, Harsha Vardhan Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

For nested-parallel computations with low depth (span, critical path length) analyzing the work, depth, and sequential cache complexity suffices to attain reasonably strong bounds on the parallel runtime and cache complexity on machine models with either shared or private caches. These bounds, however, do not extend to general hierarchical caches, due to limitations in (i) the cache-oblivious (CO) model used to analyze cache complexity and (ii) the schedulers used to map computation tasks to processors. This paper presents the parallel cache-oblivious (PCO) model, a relatively simple modification to the CO model that can be used to account for costs on a broad range of cache hierarchies. The first change is to avoid capturing artificial data sharing among parallel threads, and the second is to account for parallelism-memory imbalances within tasks. Despite the more restrictive nature of PCO compared to CO, many algorithms have the same asymptotic cache complexity bounds. The paper then describes a new scheduler for hierarchical caches, which extends recent work on "space-bounded schedulers" to allow for computations with arbitrary work imbalance among parallel subtasks. This scheduler attains provably good cache performance and runtime on parallel machine models with hierarchical caches, for nested-parallel computations analyzed using the PCO model. We show that under reasonable assumptions our scheduler is "work efficient" in the sense that the cost of the cache misses are evenly balanced across the processors-i.e., the runtime can be determined within a constant factor by taking the total cost of the cache misses analyzed for a computation and dividing it by the number of processors. In contrast, to further support our model, we show that no scheduler can achieve such bounds (optimizing for both cache misses and runtime) if work, depth, and sequential cache complexity are the only parameters used to analyze a computation.

关键词： parallel hierarchical memory Cost models Schedulers Analysis of parallel algorithms Cache complexity

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parallelizing Dynamic Information Flow Tracking 08

Parallelizing Dynamic Information Flow Tracking

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20th acm symposium on parallelism in algorithms and architectures

作者： Ruwase, Olatunji Gibbons, Phillip B. Mowry, Todd C. Ramachandran, Vijaya Chen, Shimin Kozuch, Michael Ryan, Michael Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781595939739

Dynamic information flow tracking (DIFT) is an important tool for detecting common security attacks and memory bugs. A DIFT tool tracks the flow of information through a monitored program's registers and memory locations as the program executes, detecting and containing/fixing problems on-the-fly. Unfortunately, sequential DIFT tools are quite slow, and DIFT is quite challenging to parallelize. In this paper, we present a new approach to parallelizing DIFT-like functionality. Extending our recent work on accelerating sequential DIFT, we consider a variant of DIFT that tracks the information flow only through unary operations (relaxed DIFT), and yet makes sense for detecting security attacks and memory bugs. We present a parallel algorithm for relaxed DIFT, based on symbolic inheritance tracking, which achieves linear speed-up asymptotically. Moreover, we describe techniques for reducing the constant factors, so that speed-ups can be obtained even with just a few processors. We implemented the algorithm in the context of a Log-Based architectures (LBA) system, which provides hardware support for logging a program trace and delivering it to other (monitoring) processors. Our simulation results on SPEC benchmarks and a video player show that our parallel relaxed DIFT reduces the overhead to as low as 1.2X using 9 monitoring cores on a 16-core chip multiprocessor.

关键词： dynamic information flow tracking (DIFT) program monitoring log-based monitoring parallel algorithm taint analysis

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Conflict-Free Coloring for Rectangle Ranges Using O(n^.382) Colors 07

Conflict-Free Coloring for Rectangle Ranges Using <i>O</i>(<...

引用

19th annual symposium on parallelism in algorithms and architectures

作者： Ajwani, Deepak Elbassioni, Khaled Govindarajan, Sathish Ray, Saurabh Max Planck Inst Informat Saarbrucken Germany

ISBN: (纸本)9781595936677

Given a set of points P subset of R-2, a conflict free coloring of P w.r.t. rectangle ranges is an assignment of colors to points of P, such that each non-empty axis-parallel rectangle T in the plane contains a point whose color is distinct from all other points in P boolean AND T. This notion has been the subject of recent interest, and is motivated by frequency assignment in wireless cellular networks: one naturally would like to minimize the number of frequencies (colors) assigned to bases stations (points), such that within any range (for instance, rectangle), there is no interference. We show that any set of n points in R-2 can be conflict-free colored with (O) over tilde (n(beta+epsilon)) colors in expected polynomial time, for any arbitrarily small epsilon > 0 and beta = 3-root 5/2 < 0.382. This improves upon the previously known bound of O(root n log log n/ log n).

关键词： Frequency assignment in wireless networks conflict-free coloring axis-parallel rectangles dominating sets monotone sequences

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proceedings of the annual International symposium on Microarchitecture, MICRO

Proceedings of the Annual International Symposium on Microar...

引用

47th annual IEEE/acm International symposium on Microarchitecture, MICRO 2014

The proceedings contain 53 papers. The topics discussed include: transparent hardware management of stacked DRAM as part of memory;unison cache: a scalable and effective die-stacked DRAM cache;locality-aware mapping of nested parallel patterns on GPUs;accelerating irregular algorithms on GPGPUs using fine-grain hardware worklists;exploring the design space of SPMD divergence management on data-parallel architectures;managing GPU concurrency in heterogeneous architectures;FIRM: fair and high-performance memory control for persistent memory systems;efficient memory virtualization: reducing dimensionality of nested page walks;Iso-X: a flexible architecture for hardware-managed isolated execution;cc-hunter: uncovering covert timing channels on shared processor hardware;a practical methodology for measuring the side-channel signal available to the attacker for instruction-level events;and calculating architectural vulnerability factors for spatial multi-bit transient faults.

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parallel balanced allocations 96

Parallel balanced allocations

引用

proceedings of the 1996 8th annual acm symposium on parallel algorithms and architectures

作者： Stemann, Volker Int Computer Science Inst Berkeley CA United States

ISBN: (纸本)9780897918091

We study the well known problem of throwing m balls into n bins. If each ball in the sequential game is allowed to select more than one bin, the maximum load of the bins can be exponentially reduced compared to the `classical balls into bins' game. We consider a static and a dynamic variant of a randomized parallel allocation where each ball can choose a constant number of bins. All results hold with high probability. In the static case all m balls arrive at the same time. We analyze for m = n a very simple optimal class of protocols achieving maximum load O (r√log n/log log n) if r rounds of communication are allowed. This matches the lower bound of [acmR95]. Furthermore, we generalize the protocols to the case of m>n balls. An optimal load of O(m/n) can be achieved using log log n/log(m/n) rounds of communication. Hence, for m = n log log n/log log log n balls this slackness allows to hide the amount of communication. In the `classical balls into bins' game this optimal distribution can only be achieved for m = n log n. In the dynamic variant n of the m balls arrive at the same time and have to be allocated. Each of these initial n balls has a list of m/n successor-balls. As soon as a ball is allocated its successor will be processed. We present an optimal parallel process that allocates all m = n log n balls in O(m/n) rounds. Hence, the expected allocation time is constant. The main contribution of this process is that the maximum allocation time is additionally bounded by O(log log n).

关键词： parallel algorithms

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A dynamic distributed load balancing algorithm with provable good performance 93

A dynamic distributed load balancing algorithm with provable...

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5th annual acm symposium on parallel algorithms and architectures, SPAA 1993

作者： Lüling, Reinhard Monien, Burkhard Department of Mathematics and Computer Science University of Paderborn Germany

ISBN: (纸本)0897915992

The overall efficiency of parallel algorithms is most decisively effected by the strategy applied for the mapping of workload. Strategies for balancing dynamically generated workload on a processor network which are also useful for practical applications have intensively been investigated by simulations and by direct applications. This paper presents the complete theoretical analysis of a dynamically distributed load balancing strategy. The algorithm is adaptive by nature and is therefore useful for a broad range of applications. A similar algorithmic principle has already been implemented for a number of applications in the areas of combinatorial optimization, parallel programming languages and graphical animation. The algorithm performed convincingly for all these applications. In our analysis we will prove that the expected number of packets on each processor varies only by a constant factor compared with that on any other processor, independent of the generation and consumption of workload on each processor. We give exact bounds for these values and prove an exact upper bound, independent of the number of processors. Thus, the algorithm achieves a well-balanced workload distribution on any network for any underlying application. We also prove that the variation of the expected number of packets on a processor is very small and only dependent on the parameters of the algorithm. Furthermore, we present some analysis of the costs of our algorithm. We will also show that all tradeoffs between balancing quality, variation and costs can be determined by the parameters of the algorithm. © 1993 acm.

关键词： parallel programming

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