Models of ATM communication systems were simulated on massively parallel SIMD computer. Fast simulations of ATM models are needed because the regimes of interest usually involve high volumes of traffic and low failure...
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Models of ATM communication systems were simulated on massively parallel SIMD computer. Fast simulations of ATM models are needed because the regimes of interest usually involve high volumes of traffic and low failure rates. Unexpected practical and theoretical difficulties, partly due to the massive parallelism and SIMD aspects, were encountered;this paper shows how to cope with them. In a replica-parallelsimulation of an ATM system, large variations in computed statistics are caused by small differences in the distribution of employed random number generators. A comparison of these distributions using a secondary statistical measure served to disambiguate the results.
Recently, a considerable amount of effort in the U.S. Department of Defense has been devoted to defining the High Level Architecture (HLA) for distributedsimulations. This paper describes the time management componen...
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Recently, a considerable amount of effort in the U.S. Department of Defense has been devoted to defining the High Level Architecture (HLA) for distributedsimulations. This paper describes the time management component of the HLA that defines the means by which individual simulations (called federates) advance through time. Time management includes synchronization mechanisms to ensure event ordering when this is needed. The principal challenge of the time management structure is to support interoperability among federates using different local time management mechanisms such as that used in DIS, conservative and optimistic mechanisms developed in the parallelsimulation community, and real-time hardware-in-the-loop simulations.
Many systems rely on the ability to rollback (or restore) parts of the system state to undo or recover from undesired or erroneous computations. Examples of such systems include fault tolerant systems with checkpointi...
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Many systems rely on the ability to rollback (or restore) parts of the system state to undo or recover from undesired or erroneous computations. Examples of such systems include fault tolerant systems with checkpointing, editors with undo capabilities, transaction and data base systems and optimistically synchronized parallel and distributedsimulations. An essential part of such systems is the state saving mechanism. It should not only allow efficient state saving, but also support efficient state restoration in case of roll back. Furthermore, it is often a requirement that this mechanism is transparent to the user. In this paper we present a method to implement a transparent incremental state saving mechanism in an optimistically synchronized parallel discrete event simulation system based on the Time Warp mechanism. The usefulness of this approach is demonstrated by simulations of large, detailed, realistic FCA and a DCA-like cellular phone systems.
A simulation-oriented language can significantly enhance the usability of parallel Discrete Event simulation (PDES) by hiding the complexities of the synchronization protocol used to ensure that events are processed i...
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A simulation-oriented language can significantly enhance the usability of parallel Discrete Event simulation (PDES) by hiding the complexities of the synchronization protocol used to ensure that events are processed in the correct order. The higher-level interface presented to the user by such a language also allows optimizations to be performed that are difficult and cumbersome with current parallel simulators, such as granularity control. APOSTLE is a new high-level simulation-oriented language for PDES, and in this paper we report that the APOSTLE granularity control mechanism reduced simulation run-times by as much as 80%. We also report that APOSTLE achieved a parallel speed-up of around 9 on 16 processors relative to its optimized sequential implementation and a parallel speed-up of around 6 on 16 processors relative to MODSIM II. Overall, we believe that the widespread success of PDES can only be achieved using a simulation-oriented language, and that APOSTLE has made a significant contribution towards this goal.
The proceedings contain 70 papers. The topics discussed include: programming shared virtual memory multiprocessors;parallelsimulation of a multi-dimensional computational fluid dynamics problem;computing the singular...
ISBN:
(纸本)0818673761
The proceedings contain 70 papers. The topics discussed include: programming shared virtual memory multiprocessors;parallelsimulation of a multi-dimensional computational fluid dynamics problem;computing the singular values of the product of two matrices in distributed memory multiprocessors;a latency-hiding MIMD wavelet transform;simulation of chaotic iterative processes in speed-independent computing networks;sparse householder QR factorization on a mesh;and the role of associative memory in virtual shared memory architectures: a price-performance comparison.
In this paper we study message flow processes in distributed simulators of open queueing networks. We develop and study queueing models for distributed simulators with maximum lookahead sequencing. We characterize the...
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In this paper we study message flow processes in distributed simulators of open queueing networks. We develop and study queueing models for distributed simulators with maximum lookahead sequencing. We characterize the 'external' arrival process, and the message feedback process in the simulator of a simple queueing network with feedback. We show that a certain 'natural' modelling construct for the arrival process is exactly correct, whereas an 'obvious' model for the feedback process is wrong;we then show how to develop the correct model. Our analysis throws light on the stability of distributed simulators of queueing networks with feedback. We show how the stability of such simulators depends on the parameters of the queueing network.
One of the methods used to reduce the time spent simulating VHDL designs is by parallelizing the simulation. In this paper, we describe the implementation of an object-oriented Time Warp simulator for VHDL on an actor...
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One of the methods used to reduce the time spent simulating VHDL designs is by parallelizing the simulation. In this paper, we describe the implementation of an object-oriented Time Warp simulator for VHDL on an actor based environment. The actor model of computation allows the exploitation of the grained parallelism in a truly asynchronous manner and allows for the overlap of computation with communication. Some preliminary results obtained by simulating a set of multipliers and some ISCAS benchmark circuits are provided. In addition, the importance of placing processes based on circuit partitioning techniques for improving runtimes and scalability is demonstrated. Results are reported on a Sun SPARCServer 1000 and an Intel Paragon.
The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme...
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The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. In addition we present two new partitioning algorithms both of them taking cones as fundamental units for building partitions.
ECATNets (Extended Concurrent Algebraic Term Nets) are a kind of high-level algebraic net used for specifying various aspects of distributed and parallel systems. We address the problem of developing parallel simulati...
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Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves ...
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Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallelsimulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.
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