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Inherent Limitations on Disjoint-Access parallel Implementations of Transactional Memory (Preliminary Version) 09

Inherent Limitations on Disjoint-Access Parallel Implementat...

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21st acm symposium on parallelism in algorithms and architectures

作者： Attiya, Hagit Hillel, Eshcar Milani, Alessia Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel

ISBN: (纸本)9781605586069

Transactional memory (TM) is a promising approach for designing concurrent data structures, and it is essential to develop better understanding of the formal properties that can be achieved by TM implementations. Two fundamental properties of TM implementations are disjoint-access parallelism, which is critical for their scalability, and the invisibility of read operations, which reduces memory contention. This paper proves an inherent tradeoff for implementations of transactional memories: they cannot be both disjoint-access parallel and have read-only transactions that are invisible and always terminate successfully. In fact, a lower bound of Omega(t) is proved on the number of writes needed in order to implement a read-only transaction of t items, which successfully terminates in a disjoint-access parallel TM implementation. The results assume strict serializability and thus hold under the assumption of opacity. It is shown how to extend the results to hold also for weaker consistency conditions, serializability and snapshot isolation.

关键词： Transactional memory disjoint-access parallelism partial snapshots lower bound impossibility result

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Fault-Tolerant parallel Integer Multiplication 24

Fault-Tolerant Parallel Integer Multiplication

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36th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Nissim, Roy Schwartz, Oded Spiizer, Yuval Hebrew Univ Jerusalem Dept Comp Sci Jerusalem Israel

ISBN: (纸本)9798400704161

Exascale machines have a small mean time between failures, necessitating fault tolerance. Out-of-the-box fault-tolerant solutions, such as checkpoint-restart and replication, apply to any algorithm but incur significant overhead costs. Long integer multiplication is a fundamental kernel in numerical linear algebra and cryptography. The naive, schoolbook multiplication algorithm runs in Theta(n(2)) while Toom-Cook algorithms runs in Theta(n(logk (2k -1)) for 2 <= k. We obtain the first efficient fault-tolerant parallel Toom-Cook algorithm. While asymptotically faster FFT-based algorithms exist, Toom-Cook algorithms are often favored in practice on small scale and on supercomputers. Our algorithm enables fault tolerance with negligible overhead costs. Compared to existing, general-purpose, fault-tolerant solutions, our algorithm reduces the arithmetic and communication (bandwidth) overhead costs by a factor of Theta(P/(2k -1)) (where P is the number of processors). To this end, we adapt the fault-tolerant BFS-DFS method of Birnbaum et al. (2020) for fast matrix multiplication and combine it with a coding strategy tailored for Toom-Cook. This eliminates the need for recomputations, resulting in a much faster algorithm.

关键词： Fault Tolerance Long Integer Multiplication Toom-Cook parallel Computing I/O Complexity

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Checkpoints and Continuations Instead of Nested Transactions 08

Checkpoints and Continuations Instead of Nested Transactions

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20th acm symposium on parallelism in algorithms and architectures

作者： Koskinen, Eric Herlihy, Maurice Brown Univ Dept Comp Sci Providence RI 02912 USA

ISBN: (纸本)9781595939739

We present a mechanism for partially aborting transactions through the use of data structure checkpoints and control-flow continuations. In particular, we show that boosted transactions [9] already have built-in restoration points and afford a simple, efficient implementation. Our mechanism is far simpler than previous work, which relied on complex nesting schemes to establish checkpoints. We demonstrate syntactic advantages and we quantify the overhead of checkpoints and explore several examples, illustrating the utility of partially aborting transactions. We additionally present a novel queue-based spin lock which allows threads to timeout and differ in priority. Unlike the known lock due to Craig [5], our lock is more efficient for priority schemes of few levels.

关键词： Concurrency parallel programming transactional memory boosting checkpoints continuations

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parallel algorithms for the circuit value update problem 95

Parallel algorithms for the circuit value update problem

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proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Leiserson, Charles E. Randall, Keith H. MIT Lab for Computer Science Cambridge MA United States

ISBN: (纸本)9780897917179

The circuit value update problem is the problem of updating values in a representation of a combinational circuit when some of the inputs are changed. We assume for simplicity that each combinatorial element has bounded fan-in and fan-out and can be evaluated in constant time. This problem is easily solved on an ordinary serial computer in O(W + D) time, where W is the number of elements in the altered subcircuit and D is the subcircuit's embedded depth (its depth measured in the original circuit). In this paper, we show how to solve the circuit value update problem efficiently on a P-processor parallel computer. We give a straightforward synchronous, parallel algorithm that runs in O(W/P + D lg P) expected time. Our main contribution, however, is an optimistic, asynchronous, parallel algorithm that runs in O(W/P + D + lg W + lg P) expected time, where W and D are the size and embedded depth, respectively, of the 'volatile' subcircuit, the subcircuit of elements that have inputs which either change or glitch as a result of the update. To our knowledge, our analysis provides the first analytical bounds on the running time of an optimistic algorithm.

关键词： parallel algorithms

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Low overhead parallel schedules for task graphs 90

Low overhead parallel schedules for task graphs

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SPAA '90 - proceedings of the 2nd annual acm symposium on parallel algorithms and architectures

作者： Anderson, Richard J. Beame, Paul Ruzzo, Walter L. Univ of Washington WA United States

ISBN: (纸本)0897913701

We introduce a task scheduling model which is useful in the design and analysis of algorithms for small parallel machines. We prove that under our model, the overhead experienced in scheduling an n × n grid graph is O(log log n) for p processors, p ≥ 2. We also prove a matching lower bound of Ω(log log n) for p processors, p ≥ 2. We give an extension of the model to cover the case where the processors can have varying speed or are subject to delay.

关键词： Computer programming

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An overview of cray research computers including the Y-MP/C90 and the new MPP T3D 93

An overview of cray research computers including the Y-MP/C9...

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5th annual acm symposium on parallel algorithms and architectures, SPAA 1993

作者： Oed, Wilfried Walker, Martin Cray Research GmbH Riesstrasse 25 München SO8000 Germany Cray Research Inc. 655 Lone Oak Drive EaganMN55121 United States

ISBN: (纸本)0897915992

The primary purpose of Cray Research computer systems is the timely solution of complex problems in science and engineering. A few examples illustrate that the CRAY C90 is currently the world's most powerful tool for computational science. To complement the vector-parallel architecture of the CRAY Y-MP/C90, Cray Research is developing a massively parallel processor, the CRAY T3D. The salient characteristics of this machine will be described. © 1993 acm.

关键词： parallel architectures

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parallel sorting with limited bandwidth 95

Parallel sorting with limited bandwidth

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proceedings of the 7th annual acm symposium on parallel algorithms and architectures, SPAA'95

作者： Adler, Micah Byers, John W. UC Berkeley Berkeley CA United States

ISBN: (纸本)9780897917179

We study the problem of sorting on a parallel computer with limited communication bandwidth. By using the recently proposed PRAM(m) model, where p processors communicate through a small, globally shared memory consisting of m bits, we focus on the trade-off between the amount of local computation and the amount of inter-processor communication required for parallel sorting algorithms. We prove a lower bound of Ω(n log m/m) on the time to sort n numbers in an exclusive-read variant of the PRAM (m) model. We show that Leighton's Columnsort can be used to give an asymptotically matching upper bound in the case where m grows as a fractional power of n. The bounds are of a surprising form, in that they have little dependence on the parameter p. This implies that attempting to distribute the workload across more processors while holding the problem size and the size of the shared memory fixed will not improve the optimal running time of sorting in this model. We also show that both the upper and the lower bound can be adapted to bridging models that address the issue of limited communication bandwidth: the LogP model and the BSP model. The lower bounds provide convincing evidence that efficient parallel algorithms for sorting rely strongly on high communication bandwidth.

关键词： parallel processing systems

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Optimal latency - throughput tradeoffs for data parallel pipelines 96

Optimal latency - throughput tradeoffs for data parallel pip...

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proceedings of the 1996 8th annual acm symposium on parallel algorithms and architectures

作者： Subhlok, Jaspal Vondran, Gary Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897918091

This paper addresses optimal mapping of parallel programs composed of a chain of data parallel tasks onto the processors of a parallel system. The input to this class of programs is a stream of data sets, each of which is processed in order by the chain of tasks. This computation structure, also referred to as a data parallel pipeline, is common in several application domains including digital signal processing, image processing, and computer vision. The parameters of the performance of stream processing are latency (the time to process an individual data set) and throughput (the aggregate rate at which the data sets are processed). These two criterion are distinct since multiple data sets can be pipelined or processed in parallel. We present a new algorithm to determine a processor mapping of a chain of tasks that optimizes the latency in the presence of throughput constraints, and discuss optimization of the throughput with latency constraints. The problem formulation uses a general and realistic model of inter-task communication, and addresses the entire problem of mapping, which includes clustering tasks into modules, assignment of processors to modules, and possible replication of modules. The main algorithms are based on dynamic programming and their execution time complexity is polynomial in the number of processors and tasks. The entire framework is implemented as an automatic mapping tool in the Fx parallelizing compiler for a dialect of High Performance Fortran.

关键词： parallel processing systems

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

The proceedings contain 39 papers. The topics discussed include: Fast greedy algorithms in MapReduce and streaming;reduced hardware transactions: a new approach to hybrid transactional memory;recursive design of hardware priority queues;drop the anchor: lightweight memory management for non-blocking data structures;scalable statistics counters;storage and search in dynamic peer-to-peer networks;expected sum and maximum of displacement of random sensors for coverage of a domain;on dynamics in selfish network creation;brief announcement: truly parallel burrows-wheeler compression and decompression;brief announcement: locality in wireless scheduling;brief announcement: universally truthful secondary spectrum auctions;and brief announcement: online batch scheduling for flow objectives.

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parallelism in Dynamic Well-Spaced Point Sets 11

Parallelism in Dynamic Well-Spaced Point Sets

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23rd annual symposium on parallelism in algorithms and architectures

作者： Acar, Umut A. Cotter, Andrew Hudson, Benoit Tuerkoglu, Duru Max Planck Inst Software Syst Kaiserslautern Germany

ISBN: (纸本)9781450307437

parallel algorithms and dynamic algorithms possess an interesting duality property: compared to sequential algorithms, parallel algorithms improve run-time while preserving work, while dynamic algorithms improve work but typically offer no parallelism.. Although they are often considered separately, parallel and dynamic algorithms employ similar design techniques. They both identify parts of the computation that are independent of each other. This suggests that dynamic algorithms could be parallelized to improve work efficiency while preserving fast parallel run-time. In this paper, we parallelize a dynamic algorithm for well-spaced point sets, an important problem related to mesh refinement in computational geometry. Our parallel dynamic algorithm computes a well-spaced superset of a dynamically changing set of points, allowing arbitrary dynamic modifications to the input set. On an EREW PRAM, our algorithm processes batches of k modifications such as insertions and deletions in O(k log Delta) total work and in O(log Delta) parallel time using k processors, where Delta is the geometric spread of the data, while ensuring that the output is always within a constant factor of the optimal size. EREW PRAM model is quite different from actual hardware such as modern multiprocessors. We therefore describe techniques for implementing our algorithm on modern multi-core computers and provide a prototype implementation. Our empirical evaluation shows that our algorithm can be practical, yielding a large degree of parallelism and good speedups.

关键词： parallel batch dynamic updates multithreading voronoi diagrams well-spaced point sets self-adjusting computation mesh refinement

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