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Fine-grain multithreading with the EM-X multiprocessor 97

Fine-grain multithreading with the EM-X multiprocessor

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Sohn, Andrew Kodama, Yuetsu Ku, Jui Sato, Mitsuhisa Sakane, Hirofumi Yamana, Hayato Sakai, Shuichi Yamaguchi, Yoshinori New Jersey Inst of Technology Newark NJ United States

ISBN: (纸本)9780897918909

Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multiprocessor through empirical studies. The EM-X provides hardware supports for fine-grain multithreading, including a by-passing mechanism for direct remote reads and writes, hardware FIFO thread scheduling, and dedicated instructions for generating fixed-sized communication packets. Bitonic sorting and Fast Fourier Transform are selected for experiments. Parameters that characterize the performance of multithreading are investigated, including the number of threads, the number of thread switches, the run length, and the number of remote reads. Experimental results indicate that the best communication performance occurs when the number of threads is two to four. FFT yielded over 95% overlapping due to a large amount of computation and communication parallelism across threads. Even in the absence of thread computation parallelism, multithreading helps overlap over 35% of the communication time for bitonic sorting.

关键词： parallel processing systems

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MODELS FOR USE IN THE DESIGN OF MACRO-PIPELINED parallel PROCESSORS.

MODELS FOR USE IN THE DESIGN OF MACRO-PIPELINED PARALLEL PRO...

引用

Conference proceedings - 12th annual International symposium on Computer Architecture.

作者： Smith, Bradley Warren Siegel, Howard Jay Purdue Univ Sch of Electrical Engineering West Lafayette IN USA Purdue Univ Sch of Electrical Engineering West Lafayette IN USA

ISBN: (纸本)0818606347

An approach is proposed for modeling off-the-shelf hardware and for modeling parallel algorithms, along with a design methodology to use the information provided by these models, to design a class of macro-pipelined special-purpose architectures. Nine parameters to form a model of the characteristics of parallel/distributed algorithms and the environment in which they must execute are presented. In addition, a set of tuples to model the characteristics of computer architectures is presented. By combining the tuples with the parameters, the execution time of the algorithm modeled by the parameters on the hardware modeled by the tuples can be approximated. The combination of these models could be used as a basis for computer-aided tools used in the design of macro-pipelined parallel/distributed processors.

关键词： COMPUTER SYSTEMS, DIGITAL

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Near Linear-Work parallel SDD Solvers, Low-Diameter Decomposition, and Low-Stretch Subgraphs 11

Near Linear-Work Parallel SDD Solvers, Low-Diameter Decompos...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Gupta, Anupam Koutis, Ioannis Miller, Gary L. Peng, Richard Tangwongsan, Kanat Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

This paper presents the design and analysis of a near linear-work parallel algorithm for solving symmetric diagonally dominant (SDD) linear systems. On input of a SDD n-by-n matrix A with m non-zero entries and a vector h, our algorithm computes a vector (x) over tilde;such that parallel to(x) over tilde - A(+)b parallel to A <= epsilon . parallel to A(+)b parallel to A in O(m log(O(1)) n log 1/epsilon) work and O(m(1/3+theta) log 1/epsilon) depth for any fixed theta > 0. The algorithm relies on a parallel algorithm for generating low-stretch spanning trees or spanning subgraphs. To this end, we first develop a parallel decomposition algorithm that in polylogarithmic depth and (O) over tilde vertical bar E vertical bar) work(1), partitions a graph into components with polylogarithmic diameter such that only a small fraction of the original edges are between the components. This can be used to generate low-stretch spanning trees with average stretch O(n(alpha)) in O(n(1+alpha)) work and O(n(alpha)) depth. Alternatively, it can be used to generate spanning subgraphs with polylogarithmic average stretch in O(vertical bar E vertical bar) work and polylogarithmic depth. We apply this subgraph construction to derive our solver. By using the linear system solver in known applications, our results imply improved parallel randomized algorithms for several problems, including single-source shortest paths, maximum flow, min-cost flow, and approximate max-flow.

关键词： parallel algorithms linear systems low-stretch spanning trees low-stretch subgraphs low-diameter decomposition

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parallel SYMMETRY-BREAKING IN SPARSE GRAPHS. 87

PARALLEL SYMMETRY-BREAKING IN SPARSE GRAPHS.

引用

proceedings of the nineteenth annual acm symposium on Theory of Computing.

作者： Goldberg, Andrew V. Plotkin, Serge A. Shannon, Gregory E. MIT Cambridge MA USA MIT Cambridge MA USA

ISBN: (纸本)9780897912211

We describe efficient deterministic techniques for breaking symmetry in parallel. The techniques work well on rooted trees and graphs of constant degree or genus. Our primary technique allows us to 3-color a rooted tree in O(lg n) time on an EREW PRAM using a linear number of processors. We apply these techniques to construct fast linear processor algorithms for several problems, including ( DELTA plus 1)-coloring constant-degree graphs, 5-coloring planar graphs, and finding depth-first-search trees in planar graphs. We also prove lower bounds for 2-coloring directed lists and for finding maximal independent sets in arbitrary graphs.

关键词： Computer programming

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Elimination forest guided 2D sparse LU factorization 98

Elimination forest guided 2D sparse LU factorization

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proceedings of the 1998 10th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Shen, K. Jiao, X. Yang, T. Univ of California Santa Barbara CA United States

ISBN: (纸本)9780897919890

Sparse LU factorization with partial pivoting is important for many scientific applications and delivering high performance for this problem is difficult on distributed memory machines. Our previous work has developed an approach called S* that incorporates static symbolic factorization, supernode partitioning and graph scheduling. This paper studies the properties of elimination forests and uses them to guide supernode partitioning/amalgamation and execution scheduling. The new design with 2D mapping effectively identifies dense structures without introducing too many zeros in the BLAS computation and exploits asynchronous parallelism with low buffer space cost. The implementation of this code, called S+, uses supernodal matrix multiplication which retains the BLAS-3 level efficiency and avoids unnecessary arithmetic operations. The experiments show that S+ improves our previous code substantially and can achieve up to 11.04GFLOPS on 128 Cray T3E 450 MHz nodes, which is the highest performance reported in the literature.

关键词： parallel algorithms

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Brief Announcement: Work Stealing through Partial Asynchronous Delegation 24

Brief Announcement: Work Stealing through Partial Asynchrono...

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36th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Wang, Jiawei Liu, Yutao Fu, Ming Haertig, Hermann Chen, Haibo Tech Univ Dresden Huawei Dresden Res Ctr Dresden Germany Huawei Dresden Res Ctr Dresden Germany Huawei Cent Software Inst Shenzhen Peoples R China Tech Univ Dresden Dresden Germany Shanghai Jiao Tong Univ Huawei Cent Software Inst Shanghai Peoples R China

ISBN: (纸本)9798400704161

Work stealing is a well-established technique in multi-core systems that aims to improve load balancing and task scheduling efficiency. Each processing unit maintains its own task queue, and when idle, it steals tasks from other units. Traditional work-stealing approaches face performance bottlenecks due to costly synchronization primitives and contention arising from concurrent access by both the queue owner and thieves. The state-of-the-art solution addresses these issues through coarse-grained synchronization;however, it restricts stealing in specific scenarios, thereby limiting parallelism. We introduce PadWS, a partial and asynchronous delegated work-stealing algorithm. PadWS employs a block-based design in which, under common cases, the queue owner and thieves work on separate blocks, reducing metadata contention. Delegation is partially enabled for the block in which the owner is located, allowing thieves to steal from it-an approach that deviates from the current block-based approach. Additionally, our delegation strategy is asynchronous, which removes the need for thieves to spin-wait after sending a request.

关键词： parallel processing scheduling work stealing delegation

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Optimal VLSI architectures for multidimensional DFT 89

Optimal VLSI architectures for multidimensional DFT

引用

1st annual acm symposium on parallel algorithms and architectures, SPAA 1989

作者： Bilardi, Gianfranco Hornick, Scot W. Sarrafzadeh, Majid Department of Computer Science Cornell University Upson Hall IthacaNY14853 United States Andersen Consulting Center for Strategic Tech. Res. 100 S. Wacker ChicagoIL60606 United States Dept. of Elec. Eng. and Comp. Sci. Technological Institute Northwestern University EvanstonIL60208 United States

ISBN: (纸本)089791323X

A family of VLSI architectures for computing an (n 1 × n 2 × • • " × nd)-point multidimensional D1VF (MDDFT) over Zm, the ring of integers modulo M, is presented. These architectures achieve VLSI area A = 0 ((NZlog2M)/T 2) for any comptitation time T ϵ [ω(logN),O (ωNlogM)], where N = I'Int and it is k=l assumed that logM = O(logN). A lower bound argument is developed to show that the proposed architectures are area-Time optimal. The appficability of these architectures to computation of the MDDFT over the complex field is also discussed. Using fixed-point arithmetic with b bits of precision, their area-Time performance is AT2= O(N2b 2) for any computation time T ϵ [ω(logN),O(√Nb)]. © 1989 acm.

关键词： Fixed point arithmetic

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Optimal parallel two dimensional pattern matching 93

Optimal parallel two dimensional pattern matching

引用

5th annual acm symposium on parallel algorithms and architectures, SPAA 1993

作者： Amir, Amihood Benson, Gary Farach, Martin Georgia Tech United States Department of Mathematics University of Southern California DRB 155 1024 W 36th PI Los AngelesCA90089-1113 United States DIMACS United States College of Computing Georgia Institute of Technology AtlantaGA30332-0280 United States

ISBN: (纸本)0897915992

We present a parallel algorithm for two dimensional matching. This algorithm is optimal in two ways. First, the total number of operations on the text is linear. Second, the algorithm takes time O(logm) on a CREW PRAM, thus matching the lower bound for string matching on a PRAM without concurrent writes. On a CRCW, the algorithm runs in time O(loglogro). Finding such an algorithm was a problem posed in 1985 and has been open since. © 1993 acm.

关键词： parallel algorithms

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Locating faults in a constant number of parallel testing rounds 89

Locating faults in a constant number of parallel testing rou...

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1st annual acm symposium on parallel algorithms and architectures, SPAA 1989

作者： Beigel, Richard Kosaraju, S. Rao Sullivan, Gregory F. Dept. of Computer Science Johns Hopkins University BaltimoreMD21218 United States

ISBN: (纸本)089791323X

Consider a system of processing elements in which elements may administer tests to other elements. We show, surprisingly, that a constant, number of rounds of parallel testing are sufficient to identify all faults (in all cases where fault identification is possible). We also present an O(loglogn/t t) algorithm with a small constant of proportionality, where n denotes the total number of processors and t denotes the number of faulty processors. Both of these results improve upon the previous best, which was O(log n/t t) rounds. For the problems of identifying a single faulty processor (diagnosis-with-repair) and identifying a single good processor, we present an oblivious constant-Time algorithm using a fixed 3-regular interconnect that tolerates a linear number of faults. This contrasts with the well-known result that every oblivious algorithm for complete diagnosis must use a number of rounds that is linear in t. © 1989 acm.

关键词： parallel algorithms

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Optimal parallel construction of Hamiltonian cycles and spanning trees in random graphs 93

Optimal parallel construction of Hamiltonian cycles and span...

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5th annual acm symposium on parallel algorithms and architectures, SPAA 1993

作者： MacKenzie, Philip D. Stout, Quentin F. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0897915992

We give tight bounds on the parallel complexity of some problems involving random graphs. Specifically, we show that a Hamiltonian cycle, a breadth first spanning tree, and a maximal matching can all be constructed in (logn) expected time using n/lognprocessors on the CRCW PRAM. This is a substantial improvement over the best previous algorithms, which required ((log log n)2) time and nlog2n processors. We then introduce a technique which allows us to prove that constructing an edge cover of a random graph from its adjacency matrix requires (logn) expected time on a CRCW PRAM with O(n) processors. Constructing an edge cover is implicit in constructing a spanning tree, a Hamiltonian cycle, and a maximal matching, so this lower bound holds for all these problems, showing that our algorithms are optimal. This new lower bound technique is one of the very few lower bound techniques known which apply to randomized CRCW PRAM algorithms, and it provides the first nontrivial parallel lower bounds for these problems. © 1993 acm.

关键词： Hamiltonians

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