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acm sigplan symposium on principles and practice of parallel programming

作者： Upadhyaya, Gautam Pai, Vijay S. Midkiff, Samuel P. Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781595936028

This paper presents Aspen, a high-level programming language that targets both high-productivity programming and runtime support for managing resources needed by a computation. Programs in Aspen are represented as directed graphs, where the edges are well-defined unidirectional communication channels and the nodes are instances of computational modules that process the incoming data. The resulting representation of a program closely resembles a flow chart describing the flow of computation in a server application and exposing the communication at a high level of abstraction. This strategy for program composition naturally allows parallelism and data sharing to be factored out of the core computational logic of a program, facilitating a division of labor between parallelism experts and application experts and also easing code development and maintenance. Aspen automatically and transparently supports task-level parallelism among module instances and data-level parallelism across different flows in an application or, in some cases, across different work items within a flow. Aspen automatically and adaptively allocates threads to modules according to the dynamic workload seen at those modules. Aspen is tested using a web server and a video-on-demand (VoD) server. Both servers are compared to server applications coded in other languages (such as C, C++, and Java). The Aspen programs achieve the same functionality despite using 54-96% fewer lines of user code. Nevertheless, the Aspen version always performs competitively, with performance that is always similar to or better than previous web server implementations and that sees never more than a 10% performance degradation in the VoD server. On the other hand, some workloads see superior performance with Aspen: Aspen's runtime thread allocation strategy allows the video-on-demand server to support up to 36% more simultaneous 1 Mbps video streams than a hand-tuned C++ version.

关键词： parallel programming programming languages network servers resource management

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Transactional programming in a multi-core environment 07

Transactional programming in a multi-core environment

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Adl-Tabatabai, Ali-Reza Kozyrakis, Christos Saha, Bratin Programming Systems Lab. Microprocessor Technology Lab. Intel Corporation Computer Systems Lab. Electrical Engineering Department Stanford University

ISBN: (纸本)1595936025

With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will largely be used to increase HW thread-level parallelism through higher core counts in a CMP environment. CMPs bring new challenges into the design of the software system stack. In this tutorial, we talk about the shift to multi-core processors and the programming implications. In particular, we focus on transactional programming. Transactions have emerged as a promising alternative to lock-based synchronization that eliminates many of the problems associated with lock-based synchronization. We discuss the design of both hardware and software transactional memory and quantify the tradeoffs between the different design points. We show how to extend the Java and C languages with transactional constructs, and how to integrate transactions with compiler optimizations and the language runtime (e.g., memory manager and garbage collection).

关键词： Computer programming

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Open Nesting in Software Transactional Memory 07

Open Nesting in Software Transactional Memory

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acm sigplan symposium on principles and practice of parallel programming

作者： Ni, Yang Menon, Vijay Adl-Tabatabai, Ali-Reza Hosking, Antony L. Hudson, Richard L. Moss, J. Eliot B. Saha, Bratin Shpeisman, Tatiana Intel Corp Programming Syst Lab Santa Clara CA 95054 USA

ISBN: (纸本)9781595936028

Transactional memory (TM) promises to simplify concurrent programming while providing scalability competitive to fine-grained locking. Language-based constructs allow programmers to denote atomic regions declaratively and to rely on the underlying system to provide transactional guarantees along with concurrency. In contrast with fine-grained locking, TM allows programmers to write simpler programs that are composable and deadlock-free. TM implementations operate by tracking loads and stores to memory and by detecting concurrent conflicting accesses by different transactions. By automating this process, they greatly reduce the programmer's burden, but they also are forced to be conservative. In certain cases, conflicting memory accesses may not actually violate the higher-level semantics of a program, and a programmer may wish to allow seemingly conflicting transactions to execute concurrently. allow seemingly conflicting transactions to execute concurrently. Open nested transactions enable expert programmers to differentiate between physical conflicts, at the level of memory, and logical conflicts that actually violate application semantics. A TM system with open nesting can permit physical conflicts that are not logical conflicts, and thus increase concurrency among application threads. Here we present an implementation of open nested transactions in a Java-based software transactional memory (STM) system. We describe new language constructs to support open nesting in Java, and we discuss new abstract locking mechanisms that a programmer can use to prevent logical conflicts. We demonstrate how these constructs can be mapped efficiently to existing STM data structures. Finally, we evaluate our system on a set of Java applications and data structures, demonstrating how open nesting can enhance application scalability.

关键词： transactional memory nested transactions open nesting abstract locks

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parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Fang, Jesse Z. Programming Systems Lab. Intel Corporation

ISBN: (纸本)1595936025

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraints increase with frequency, multi-core or many-core microprocessors will be the way of the future. In the near future, hardware platforms will have sixteen or more cores on die to achieve more than one Tera Instructions Per second (TIPs) computation power. These cores will communicate each other through an on-die interconnect fabric with more than one TB/s on-die bandwidth and less than 30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and optical silicon photonics will provide up to one Tb/s I/O bandwidth between boxes. The hardware system with TIPs of compute power operating on terabytes of data make this a ?tera-scale? platform. What are the software implications with the hardware changes from uniprocessor to tera-scale platform with many cores as "the way of the future?" It will be a great challenge for programming environments to help programmers develop concurrent code for most client software. A good concurrent programming environment should extend existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are many research topics. Examples topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms such as Transactional Memory to replace simple ?Thread + Lock? structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with hardware support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and software tools in the concurrent programming environment. A more interesting proble

关键词： parallel programming

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Adaptive Work Stealing with parallelism Feedback 07

Adaptive Work Stealing with Parallelism Feedback

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acm sigplan symposium on principles and practice of parallel programming

作者： Agrawal, Kunal He, Yuxiong Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781595936028

We present an adaptive work-stealing thread scheduler, A-STEAL, for fork-join multithreaded jobs, like those written using the Cilk multithreaded language or the Hood work-stealing library. The A-STEAL algorithm is appropriate for large parallel servers where many jobs share a common multiprocessor resource and in which the number of processors available to a particular job may vary during the job's execution. A-STEAL provides continual parallelism feedback to a job scheduler in the form of processor requests, and the job must adapt its execution to the processors allotted to it. Assuming that the job scheduler never allots any job more processors than requested by the job's thread scheduler, A-STEAL guarantees that the job completes in near-optimal time while utilizing at least a constant fraction of the allotted processors. Our analysis models the job scheduler as the thread scheduler's adversary, challenging the thread scheduler to be robust to the system environment and the job scheduler's administrative policies. We analyze the performance of A-STEAL using "trim analysis," which allows us to prove that our thread scheduler performs poorly on at most a small number of time steps, while exhibiting near-optimal behavior on the vast majority. To be precise, suppose that a job has work T-1 and span (critical-path length) T-infinity. On a machine with P processors, A-STEAL completes the job in expected O(T-1/(P) over tilde + T-infinity + L lg P) time steps. where L is the length of a scheduling quantum and (P) over tilde denotes the O(T-infinity + L lg P)-trimined availability. This quantity is the average of the processor availability over all but the O(T-infinity + L lg P) time steps having the highest processor availability. When the job's parallelism dominates the trimmed availability, that is, (P) over tilde << T-1/T-infinity, the job achieves nearly perfect linear speedup. Conversely, when the trimmed mean dominates the parallelism, the asymptotic running time

关键词： Adaptive scheduling Adversary Critical path Distributed scheduling Job scheduling Multithreaded Languages Multiprocessing Multiprogramming parallelism feedback parallel computation Processor allocation Space sharing Span Thread scheduling Two-level scheduling Trim analysis Work Work stealing

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X10: Concurrent programming for modern architectures 07

X10: Concurrent programming for modern architectures

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Saraswat, Vijay A. Sarkar, Vivek Von Praun, Christoph IBM TJ Watson Research Center

ISBN: (纸本)1595936025

Two major trends are converging to reshape the landscape of concurrent object-oriented programming languages. First, trends in modern architectures (multi-core, accelerators, high performance clusters such as Blue Gene) are making concurrency and distribution inescapable for large classes of OO programmers. Second, experience with first-generation concurrent OO languages (e.g. Java threads and synchronization) have revealed several drawbacks of unstructured threads with lock-based synchronization. X10 is a second generation OO language designed to address both programmer productivity and parallel performance for modern architectures. It extends sequential Java with a handful of constructs for concurrency and distribution. It introduces a clustered address space to deal with distribution. A computation is thought of as running at multiple places, with many simultaneous activities operating in each place. Objects and activities once created in a particular place stay confined to that place. However, a data-structure (object) allocated in one place may contain a reference to an object allocated in anoter place. (Thus X10 supports a partitioned global address space. X10 is an explicitly concurrent language. It provides constructs for lightweight asynchrony, making it easy for programmers to write code for target architectures that provide massive parallelism. It provides for recursive fork-join parallelism for structured concurrency. It provides for termination detection so that collections of activities may be reliably sequenced (even if they run across multiple places). It provides for a very simple form of atomic blocks in lieu of locks for mutual exclusion. These constructs can be used to define more sophisticated synchronization constructs such as futures and clocks. X10 supports a rich notion of multi-dimensional index spaces (regions), together with a rich set of operations on regions. Regions are first-class data-structures - they can be produced dynamically, st

关键词： Concurrent engineering

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Compiler-directed energy optimization for parallel-disk-based systems

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2007年第9期18卷 1241-1257页

作者： Son, Seung Woo Chen, Guangyu Ozturk, Ozcan Kandemir, Mahmut Choudhary, Alok Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Microsoft Corp Redmond WA 98052 USA Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural-level techniques to reduce disk power by taking advantage of idle periods experienced by disks. Although such techniques have been known to be effective in certain cases, they share a common drawback: They operate in a reactive manner, i.e., they control disk power by observing past disk activity (for example, idle and active periods) and estimating future ones. Consequently, they can miss opportunities for saving power and incur significant performance penalties due to inaccuracies in predicting idle and active times. Motivated by this observation, this paper proposes and evaluates a compiler-driven approach to reducing disk power consumption of array-based scientific applications executing on parallel architectures. The proposed approach exposes disk layout information to the compiler, allowing it to derive the disk access pattern, i.e., the order in which parallel disks are accessed. This paper demonstrates two uses of this information. First, we can implement proactive disk power management, i.e., we can select the most appropriate power-saving strategy and disk-preactivation strategy based on the compiler-predicted future idle and active periods of parallel disks. Second, we can restructure the application code to increase the length of idle disk periods, which leads to better exploitation of available power-saving capabilities. We implemented both these approaches within an optimizing compiler and tested their effectiveness using a set of benchmark codes from the Spec 2000 suite and a disk power simulator. Our results show that the compiler-driven disk power management is very promising. The experimental results also reveal that, although proactive disk power management is very effective, code restructuring for disk power achieves additional energy savings across all the benchmarks tested, and these savings a

关键词： disk subsystem I/O traces optimizing compilers power-aware computing parallel I/O

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Session details: parallel applications 07

Session details: Parallel applications

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proceedings of the 12th acm sigplan symposium on principles and practice of parallel programming

作者： P. Sadayappan Ohio State University

No abstract available.

ISBN: (纸本)9781595936028

No abstract available.

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proceedings of the 2006 acm sigplan symposium on principles and practice of parallel programming, PPOPP'06

Proceedings of the 2006 ACM SIGPLAN Symposium on Principles ...

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2006 acm sigplan symposium on principles and practice of parallel programming, PPOPP'06

ISBN: (纸本)1595931899

The proceedings contain 27 papers. The topics discussed include: parallel programming and code selection in fortress;collective communication on architectures that support simultaneous communication over multiple links;performance evaluation of adaptive MPI;mobile MPI programs in computational grid;RDMA read based rendezvous protocol for MPI over InfiniBand: design alternatives and benefits;programming for parallelism and locality with hierarchically tiled arrays;parallel programming in modern web search engines;on-line automated performance diagnosis on thousands of processes;a case study in top-down performance estimation for a large-scale parallel application;adaptive scheduling with parallelism feedback;predicting bounds on queuing delay for batch-scheduled parallel machines;optimizing irregular shared-memory applications for distributed memory systems;and scalable synchronous queues.

关键词： parallel processing systems

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The Z-polyhedral model 07

The Z-polyhedral model

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proceedings of the 12th acm sigplan symposium on principles and practice of parallel programming

作者： Gautam Gupta Sanjay Rajopadhye Colorado State University Fort Collins CO and INRIA-Rennes France Colorado State University Fort Collins CO

ISBN: (纸本)9781595936028

The polyhedral model is a well developed formalism and has been extensively used in a variety of contexts viz. the automatic parallelization of loop programs, program verification, locality, hardware generationand more recently, in the automatic reduction of asymptotic program complexity. Such analyses and transformations rely on certain closure properties. However, the model is limited in expressivity and the need for a more general class of programs is widely *** provide the extension to ⁰-polyhedra which are the intersection of polyhedra and lattices. We prove the required closure properties using a novel representation and interpretation of ⁰-polyhedra. In addition, we also prove closure in the ⁰-polyhedral model under images by dependence functions---thereby proving that unions of LBLs, widely assumedto be a richer class of sets, is equal to unions of ⁰-polyhedra. Another corollary of this result is the equivalence of the unions of ⁰-polyhedraand Presburger sets. Our representation and closure properties constitute the foundations of the ⁰-polyhedral model. As an example, we presentthe transformation for automatic reduction of complexity in the ⁰-polyhedral model.

关键词： program transformation models of computations loop optimization equational programming

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