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Static analysis of atomicity for programs with non-blocking synchronization 05

Static analysis of atomicity for programs with non-blocking ...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Wang, Liqiang Stoller, Scott D. Department of Computer Science State University of New York at Stony Brook Stony Brook NY 11794 United States

ISBN: (纸本)9781595930804

In concurrent programming, non-blocking synchronization is very efficient but difficult to design correctly. This paper presents a static analysis to show that code blocks are atomic, i.e., that every execution of the program is equivalent to one in which those code blocks execute without interruption by other threads. Our analysis determines commutativity of operations based primarily on how synchronization primitives (including locks, load-linked, store-conditional, and compare-and-swap) are used. A reduction theorem states that certain patterns of commutativity imply atomicity. Atomicity is itself an important correctness requirement for many concurrent programs. Furthermore, an atomic code block can be treated as a single transition during subsequent analysis of the program;this can greatly improve the efficiency of the subsequent analysis. We demonstrate the effectiveness of our approach on several concurrent non-blocking programs. Copyright 2005 acm.

关键词： parallel processing systems

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Extracting SMP parallelism for dense linear algebra algorithms from high-level specifications 05

Extracting SMP parallelism for dense linear algebra algorith...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Low, Tze Meng Van De Geijn, Robert A. Van Zee, Field G. Department of Computer Sciences University of Texas at Austin Austin TX 78712

ISBN: (纸本)9781595930804

We show how to exploit high-level information, available as part of the derivation of provably correct algorithms, so that SMP parallelism can be systematically identified. Recent research has shown that loop-based dense linear algebra algorithms can be systematically derived from the mathematical specification of the operation. Fundamental to the methodology is the determination of loop-invariants (in the sense of Dijkstra and Hoare) from which correct loops can be systematically derived. We show how the high-level specification of the operation together with these loop-invariants can be exploited to detect the independence of loop iterations. This in turn then allows a Workqueuing Model to be used to implement and parallelize the algorithms using a feature proposed for OpenMP 3.0, task queues. Although performance is not the main feature of this paper, performance is reported on a 4 CPU Itanium2 server for a concrete example, the symmetric rank-k update operation. Copyright 2005 acm.

关键词： parallel processing systems

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A novel approach for partitioning iteration spaces with variable densities 05

A novel approach for partitioning iteration spaces with vari...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Kejariwal, Arun Nicolau, Alexandra Banerjee, Utpal Polychronopoulos, Constantine D. Center for Embedded Computer Systems University of California at Irvine Irvine CA United States Intel Corporation Santa Clara CA United States Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana IL United States

ISBN: (纸本)9781595930804

Efficient partitioning of parallel loops plays a critical role in high performance and efficient use of multiprocessor systems. Although a significant amount of work has been done in partitioning and scheduling of loops with rectangular iteration spaces, the problem of partitioning non-rectangular iteration spaces - e.g., triangular, trapezoidal iteration spaces - with variable densities has not been addressed so far to the best of our knowledge. In this paper, we present a mathematical model for partitioning N-dimensional non-rectangular iteration spaces with variable densities. We present a unimodular loop transformation and a geometric approach for partitioning an iteration space along an axis corresponding to the outermost loop across a given number of processors to achieve near-optimal performance, i.e., to achieve nearoptimal load balance across different processors. We present a case study to illustrate the effectiveness of our approach. Copyright 2005 acm.

关键词： parallel processing systems

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An evaluation of global address space languages: Co-array fortran and Unified parallel C 05

An evaluation of global address space languages: Co-array fo...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Coarfa, Cristian Dotsenko, Yuri Mellor-Crummey, John Cantonnet, François Ei-Ghazawi, Tarek Mohanti, Ashrujit Yao, Yiyi Chavarría-Miranda, Daniel Rice University Houston TX George Washington University Washington DC Pacific Northwest National Laboratory Richland WA

ISBN: (纸本)9781595930804

Co-array Fortran (CAP) and Unified parallel C (UPC) are two emerging languages for single-program, multiple-data global address space programming. These languages boost programmer productivity by providing shared variables for inter-process communication instead of message passing. However, the performance of these emerging languages still has room for improvement. In this paper, we study the performance of variants of the NAS MG, CG, SP, and BT benchmarks on several modern architectures to identify challenges that must be met to deliver top performance. We compare CAF and UPC variants of these programs with the original Fortran+MPI code. Today, CAF and UPC programs deliver scalable performance on clusters only when written to use bulk communication. However, our experiments uncovered some significant performance bottlenecks of UPC codes on all platforms. We account for the root causes limiting UPC performance such as the synchronization model, the communication efficiency of strided data, and source-to-source translation issues. We show that they can be remedied with language extensions, new synchronization constructs, and, finally, adequate optimizations by the back-end C compilers. Copyright 2005 acm.

关键词： Computer programming languages

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Exposing speculative thread parallelism in SPEC2000 05

Exposing speculative thread parallelism in SPEC2000

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Prabhu, Manohar K. Olukotun, Kunle Stanford University Computer Systems Laboratory Stanford CA 94305

ISBN: (纸本)9781595930804

As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance the performance of chip multiprocessors that has received considerable attention is the use of thread-level speculation (TLS). As a case study, we manually parallelized several of the SPEC CPU2000 floating point and integer applications using TLS. The use of manual parallelization enabled us to apply techniques and programmer expertise that are beyond the current capabilities of automated parallelizers. With the experience gained from this, we provide insight into ways to aggressively apply TLS to parallelize applications for high performance. This information can help guide future advanced TLS compiler design. For each application, we discuss how and where parallelism was located within the application, the impediments to extracting this parallelism using TLS, and the code transformations that were required to overcome these impediments. We also generalize these experiences to a discussion of common hindrances to TLS parallelization, and describe methods of programming that help expose application parallelism to TLS systems. These guidelines can assist developers of uniprocessor programs to create applications that can easily port to TLS systems and yield good performance. By using manual parallelization on SPEC2000, we provide guidance on where thread-level parallelism exists in these well known benchmarks, what limits its extraction, how to reduce these limitations and what performance can be expected on these applications from a chip multiprocessor system with TLS. Copyright 2005 acm.

关键词： parallel processing systems

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Scaling model checking of dataraces using dynamic information 05

Scaling model checking of dataraces using dynamic informatio...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Shacham, Ohad Sagiv, Mooly Schuster, Assaf School of Computer Science Tel Aviv University IBM Haifa Research Lab. School of Computer Science Tel Aviv University Computer Science Department Technion

ISBN: (纸本)9781595930804

Dataraces in multithreaded programs often indicate severe bugs and can cause unexpected behaviors when different thread interleavings are executed. Because dataraces are a cause for concern, many works have dealt with the problem of detecting them. Works based on dynamic techniques either report errors only for dataraces that occur in the current interleaving, which limits their usefulness, or produce many spurious dataraces. Works based on model checking search exhaustively for dataraces and thus can reveal even those that occur in rarely executed paths. However, the applicability of model checking is limited because the large number of thread interleavings in realistic multithreaded programs causes state space explosion. In this work, we combine the two techniques in a hybrid scheme which overcomes these difficulties and enjoys the advantages of both worlds. Our hybrid technique succeeds in providing thread interleavings that prove the existence of dataraces in realistic programs. The programs we experimented with cannot be checked using either an ordinary industrial strength model checker or bounded model checking. Copyright 2005 acm.

关键词： Computer programming

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Using multiple energy gears in MPI programs on a power-scalable cluster 05

Using multiple energy gears in MPI programs on a power-scala...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Freeh, Vincent W. Pan, Feng Kappiah, Nandini Lowenthal, David K. Department of Computer Science North Carolina State University Raleigh NC United States Department of Computer Science University of Georgia Athens GA United States

ISBN: (纸本)9781595930804

Recently, system architects have built low-power, high-performance clusters, such as Green Destiny. The idea behind these clusters is to improve the energy efficiency of nodes. However, these clusters save power at the expense of performance. Our approach is instead to use high-performance cluster nodes that are frequency-and voltage-scalable;energy can than be saved by scaling down the CPU. Our prior work has examined the costs and benefits of executing an entire application at a single reduced frequency. This paper presents a framework for executing a single application in several frequency-voltage settings. The basic idea is to first divide programs into phases and then execute a series of experiments, with each phase assigned a prescribed frequency. During each experiment, we measure energy consumption and time and then use a heuristic to choose the assignment of frequency to phase for the next experiment. Our results show that significant energy can be saved without an undue performance penalty;particularly, our heuristic finds assignments of frequency to phase that is superior to any fixed-frequency solution. Specifically, this paper shows that more than half of the NAS benchmarks exhibit a better energy-time tradeoff using multiple gears than using a single gear. For example, IS using multiple gears uses 9% less energy and executes in 1% less time than the closest single-gear solution. Compared to no frequency scaling, multiple gear IS uses 16% less energy while executing only 1% longer. Copyright 2005 acm.

关键词： Computer programming

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Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems 05

Exposing disk layout to compiler for reducing energy consump...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Son, S.W. Chen, G. Kandemir, M. Choudhary, A. CSE Department Pennsylvania State University University Park PA 16802 United States ECE Department Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781595930804

Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduce disk power by taking advantage of idle periods experienced by disks. While such techniques have been known to be effective in certain cases, they share a common drawback: they operate in a reactive manner;i.e., they control disk power by observing past disk activity (e.g., idle and active periods) and estimating future ones. Consequently, they can miss opportunities for saving power and incur significant performance penalties, due to inaccuracies in predicting idle and active times. Motivated by this observation, this paper proposes and evaluates a compiler-driven approach to reducing disk power consumption of array-based scientific applications executing on parallel architectures. The proposed approach exposes disk layout information to the compiler, allowing it to derive disk access pattern, i.e., the order in which parallel disks are accessed. This paper demonstrates two uses of this information. First, we can do proactive disk power management, i.e., we can select the most appropriate power-saving strategy and disk preactivation strategy based on the compiler-predicted future idle and active periods of parallel disks. Second, we can restructure the application code to increase length of idle periods, which leads to better exploitation of available power-saving capabilities. We implemented both these approaches within an optimizing compiler and tested their effectiveness using a set of benchmark codes from the Spec2000 suite and a disk power simulator. Our results show that the compiler-driven disk power management is very promising. The experimental results also reveal that, while proactive disk power management is very effective, code restructuring for disk power achieves the best energy savings across all the benchmarks tested. Copyright 2005 acm.

关键词： Program compilers

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proceedings of the acm sigplan symposium on principles and Pracice of parallel programming, PPOPP: Preface

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

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proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 2005年 iii页

作者： Yelick, Katherine Grimshaw, Andrew

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Effective communication coalescing for data-parallel applications 05

Effective communication coalescing for data-parallel applica...

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proceedings of the tenth acm sigplan symposium on principles and practice of parallel programming

作者： Daniel Chavarría-Miranda John Mellor-Crummey Pacific Northwest National Laboratory (PNNL) Rice University

ISBN: (纸本)9781595930804

Communication coalescing is a static optimization that can reduce both communication frequency and redundant data transfer in compiler-generated code for regular, data parallel applications. We present an algorithm for coalescing communication that arises when generating code for regular, data-parallel applications written in High Performance Fortran (HPF). To handle sophisticated computation partitionings, our algorithm normalizes communication before attempting coalescing. We experimentally evaluate our algorithm, which is implemented in the dHPF compiler, in the compilation of HPF versions of the NAS application benchmarks SP, BT and LU. Our normalized coalescing algorithm improves the performance and scalability of compiler-generated code for these benchmarks by reducing the communication volume up to 55% compared to a simpler coalescing strategy and enables us to match the communication volume and frequency in hand-optimized MPI implementations of these codes.

关键词： communication analysis and optimization data-parallelism high-performance fortran (HPF) parallel languages

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