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programming the FlexRAM parallel intelligent memory system

acm sigplan NOTICES 2003年第10期38卷 49-60页

作者： Fraguela, BB Renau, J Feautrier, P Padua, D Torrellas, J Univ A Coruna Dept Elect & Sistemas Coruna Spain Univ Illinois Dept Comp Sci Urbana IL 61801 USA Ecole Normale Super Lyon LIP F-69364 Lyon France

In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able to exploit computation in the main memory. While several instantiations of this architecture have been proposed, the question of how to effectively program them with little effort has remained a major challenge. In this paper, we show how to effectively hand-program an intelligent memory architecture at a high level and with very modest effort. We use FlexRAM as a prototype architecture. To program it, we propose a family of high-level compiler directives inspired by OpenMP called CFlex. Such directives enable the processors in memory to execute the program in cooperation with the main processor. In addition, we propose libraries of highly-optimized functions called Intelligent Memory Operations (IMOs). These functions program the processors in memory through CFlex, but make them completely transparent to the programmer. Simulation results show that, with CFlex and IMOs, a server with 64 simple processors in memory runs on average 10 times faster than a conventional server. Moreover, a set of conventional programs with 240 lines on average are transformed into CFlex parallel form with only 7 CFlex directives and 2 additional statements on average.

关键词： languages intelligent memory architecture compiler directives programming heterogeneous computers parallel languages

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Exploiting high-level coherence information to optimize distributed shared state

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acm sigplan NOTICES 2003年第10期38卷 131-142页

作者： Chen, DQ Tang, CQ Sanders, B Dwarkadas, S Scott, ML Univ Rochester Dept Comp Sci Rochester NY 14627 USA

InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating systems, and programming languages. As a complement to RPC/RMI, InterWeave facilitates the rapid development of maintainable code by allowing processes to access shared data using ordinary reads and writes. Internally, InterWeave employs a variety of aggressive optimizations to obtain significant performance improvements with minimal programmer effort. In this paper, we focus on application-specific optimizations that exploit dynamic high-level information about an application's spatial data access patterns and the stringency of its coherence requirements. Using applications drawn from computer vision, datamining, and web proxy caching, we illustrate the specification of coherence requirements based on the (temporal) concept of "recent enough" to use, and introduce two (spatial) notions of views, which allow a program to limit coherence management to the portion of a data structure actively in use. Experiments with these applications show that InterWeave can reduce their communication traffic by up to one order of magnitude with minimum effort on the part of the application programmer.

关键词： Computer systems programming

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Exploiting task-level concurrency in a programmable network interface 03

Exploiting task-level concurrency in a programmable network ...

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proceedings of the ninth acm sigplan symposium on principles and practice of parallel programming

作者： Hyong-youb Kim Vijay S. Pai Scott Rixner Rice University

ISBN: (纸本)9781581135886

Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. This paper aims to offset those performance disadvantages by exploiting task-level concurrency in the workload to parallelize the network interface firmware for a programmable controller with two processors. By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip storage. Compared to the uniprocessor firmware released by the manufacturer, the parallelized network interface firmware increases throughput by 65% for bidirectional UDP traffic of maximum-sized packets, 157% for bidirectional UDP traffic of minimum-sized packets, and 32--107% for real network services. This parallelization results in performance within 10--20% of a modern ASIC-based network interface for real network services.

关键词： firmware programmable network interface ethernet parallel programming

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Impala: a middleware system for managing autonomic, parallel sensor systems

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acm sigplan NOTICES 2003年第10期38卷 107-118页

作者： Liu, T Martonosi, M Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in some cases, actuate control mechanisms in response. Like traditional parallel systems, communication between nodes is of fundamental importance, but is typically accomplished via wireless transceivers. One further key attribute of sensor networks is that they are almost always long-running systems, intended to operate in situ, with minimal direct human intervention, for months or years. This requirement for long-running autonomy mandates careful design of the runtime system that manages applications on each node, to ensure reliability and ease of upgrades over the life of the system. This paper describes Impala, a middleware architecture that enables application modularity, adaptivity, and repair-ability in wireless sensor networks. Impala allows software updates to be received via the node's wireless transceiver and to be applied to the running system dynamically. In addition, Impala also provides an interface for on-the-fly application adaptation in order to improve the performance, energy-efficiency, and reliability of the software system. Impala has been designed to be a part of the ZebraNet mobile sensor network, but we are also prototyping it within HP/Compaq iPAQ Pocket PC handhelds. We present performance data for both real system measurements of the Pocket PC version as well as simulations of a full mobile sensor system deployment. Overall, Impala is a lightweight runtime system that can greatly improve system reliability, performance, and energy-efficiency. The ideas introduced here for sensor networks have applicability more broadly in other long-running autonomous parallel systems as well.

关键词： design experimentation performance sensor networks middleware system software adaptation software update

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parallel programming challenges for Internet-scale computing (Entropia) 01

Parallel programming challenges for Internet-scale computing...

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8th acm sigplan symposium on principles and practice of parallel programming

作者： Chien, A.A. Entropia Inc. University of California San Diego CA United States

No abstract available.

ISBN: (纸本)9781581133462

No abstract available.

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parallel computing in 2010: Opportunities and challenges in a networked world 01

Parallel computing in 2010: Opportunities and challenges in ...

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8th acm sigplan symposium on principles and practice of parallel programming

作者： Foster, I. Argonne National Laboratory and University of Chicago

No abstract available.

ISBN: (纸本)9781581133462

No abstract available.

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Proceeding of the acm sigplan symposium on principles and practice of parallel programming, PPOPP

Proceeding of the ACM SIGPLAN symposium on principles and pr...

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8th acm sigplan symposium on principles and practice of parallel programming

The proceedings contains 14 papers from the conference on the proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP. Topics discussed include: reference idempotency analysis: a framework for optimizing speculative execution;pointer and escape analysis for multithread programs;language support for motion-order matrices;efficient load balancing for wide-area divide-and-conquer applications;scalable queue-based spin locks with timeout;contention ellimination by replication of sequential sections in distributed shared memory programs;and accurate data redistribution cost estimation in software distributes shared memory systems.

关键词： parallel processing systems

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Pointer and escape analysis for multithreaded programs 01

Pointer and escape analysis for multithreaded programs

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8th acm sigplan symposium on the principles and practice of parallel Computing

作者： Salcianu, A Rinard, M MIT Comp Sci Lab Cambridge MA 02139 USA

ISBN: (纸本)9781581133462

This paper presents a new combined pointer and escape analysis for multithreaded programs. The algorithm uses a new abstraction called parallel interaction graphs to analyze the interactions between threads and extract precise points-to, escape, and action ordering information for objects accessed by multiple threads. The analysis is compositional, analyzing each method or thread once to extract a parameterized analysis result that can be specialized for use in any context. It is also capable of analyzing programs. that use the unstructured form of multithreading present in languages such as Java and standard threads packages such as POSIX threads. We have implemented the analysis in the MIT Flex compiler for Java and used the extracted information to 1) verify that programs correctly use region-based allocation constructs, 2) eliminate dynamic checks associated with the use of regions, and 3) eliminate unnecessary synchronization. Our experimental results show that analyzing the interactions between threads significantly increases the effectiveness of the region analysis and region check elimination, but has little effect for synchronization elimination.

关键词： THREADS Multithreading Java Java programming language Pointer Unix operating system Escape Analysis

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LogGPS: A parallel computational model for synchronization analysis 01

LogGPS: A parallel computational model for synchronization a...

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8th acm sigplan symposium on the principles and practice of parallel Computing

作者： Ino, F Fujimoto, N Hagihara, K Osaka Univ Grad Sch Engn Sci Osaka 5608531 Japan

ISBN: (纸本)9781581133462

We present a new parallel computational model, named Log-GPS, which captures synchronization. The LogGPS model is an extension of the LogGP model, which abstracts communication on parallel platforms. Although the LogGP model captures long messages with one bandwidth parameter (G), it does not capture synchronization that is needed before sending a long message by high-level communication libraries. Our model has one additional parameter, S, defined as the threshold for message length, above which synchronous messages are sent. We also present some experimental results using both models. The results include (1) a verification of the LogGPS model, (2) an example of synchronization analysis using an MPI program and (3) a comparison of the models. The results indicate that the LogGPS model is more accurate than the LogGP model, and analyzing synchronization costs is important when improving parallel program performance.

关键词： parallel processing systems

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Statistical scalability analysis of communication operations in distributed applications 01

Statistical scalability analysis of communication operations...

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8th acm sigplan symposium on the principles and practice of parallel Computing

作者： Vetter, JS McCracken, MO Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781581133462

Current trends in high performance computing suggest that users will soon have widespread access to clusters of multiprocessors with hundreds, if not thousands, of processors. This unprecedented degree of parallelism will undoubtedly expose scalability limitations in existing applications, where scalability is the ability of a parallel algorithm on a parallel architecture to effectively utilize an increasing number of processors. Users will need precise and automated techniques for detecting the cause of limited scalability. This paper addresses this dilemma. First, we argue that users face numerous challenges in understanding application scalability: managing substantial amounts of experiment data, extracting useful trends from this data, and reconciling performance information with their application's design. Second, we propose a solution to automate this data analysis problem by applying fundamental statistical techniques to scalability experiment data. Finally, we evaluate our operational prototype on several applications, and show that statistical techniques offer an effective strategy for assessing application scalability. In particular, we find that non-parametric correlation of the number of tasks to the ratio of the time for communication operations to overall communication time provides a reliable measure for identifying communication operations that scale poorly.

关键词： Scalability Experimental data statistical techniques Consumers Communication Research Automated recording parallel architectures Surgery Multiprocessor High Performance Computing parallel algorithms

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