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检索条件"任意字段=Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures"

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Scheduling Strategies for Optimistic parallel Execution of Irregular Programs 08

Scheduling Strategies for Optimistic Parallel Execution of I...

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20th acm symposium on parallelism in algorithms and architectures

作者： Kulkarni, Milind Carribault, Patrick Pingali, Keshav Ramanarayanan, Ganesh Walter, Bruce Bala, Kavita Chew, L. Paul Univ Texas Austin Austin TX 78712 USA Cornell Univ Ithaca NY USA

ISBN: (纸本)9781595939739

Recent application studies have shown that many irregular applications have a generalized data parallelism that manifests itself as iterative computations over worklists of different kinds. In general, there are complex dependencies between iterations. These dependencies cannot be elucidated statically because they depend on the inputs to the program;thus, optimistic parallel execution is the only tractable approach to parallelizing these applications. We have built a system called Galois that supports this style of parallel execution. Its main features are (i) set iterators for expressing worklist-based data parallelism, and (ii) a runtime system that performs optimistic parallelization of these iterators, detecting conflicts and rolling back computations as needed. Our work builds on the Galois system, and it addresses the problem of scheduling iterations of set iterators on multiple cores. The policy used by the base Galois system is to assign an iteration to a core whenever it needs work to do, but we show in this paper that this policy is not optimal for many applications. We also argue that OpenMP-style DO-ALL loop scheduling directives such as chunked and guided self-scheduling are too simplistic for irregular programs. These difficulties led us to develop a general scheduling framework for irregular problems;OpenMP-style scheduling strategies are special cases of this general approach. We also provide hooks into our framework, allowing the programmer to leverage application knowledge to further tune a schedule for a particular application. To evaluate this framework, we implemented it as an extension of the Galois system. We then tested the system using five real-world, irregular, data-parallel applications. Our results show that (i) the optimal scheduling policy can be different for different applications and often leverages application-specific knowledge and (ii) implementing these schedules in the Galois system is relatively straightforward.

关键词： Optimistic parallelism Irregular Programs Scheduling

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architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins 41

Architectures and algorithms for millisecond-scale molecular...

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2008 - 41st annual IEEE/acm International symposium on Microarchitecture, MICRO-41

作者： Shaw, David E. Columbia's Medical School United States

ISBN: (纸本)9781424428366

The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle lead to important scientific advances and provide a powerful new tool for drug discovery. A wide range of biologically interesting phenomena, however, occur over time scales on the order of a millisecond - several orders of magnitude beyond the duration of the longest current MD simulations. Our research group is currently building a specialized, massively parallel machine, called Anton, which should soon be capable of executing millisecond-scale MD simulations of proteins at an atomic level of detail. Anton's highly accelerated execution of such simulations is attributable in large part to specialized logic for the high-speed calculation of pairwise interactions between particles and/or gridpoints separated by no more than some specified cutoff radius. In particular, each of Anton's 512 ASICs, which are implemented using 90-nm technology, includes a "high-throughput interaction subsystem" incorporating 32 highly specialized pipelines running at 800 MHz. During every cycle, each of these pipelines produces a pairwise-interaction result that would require approximately 50 arithmetic operations to calculate on a general-purpose processor. Novel algorithms and architectural features are used to greatly reduce the requirements for inter- and intra-chip communication, allowing Anton to feed these pipelines and collect their results at a speed sufficient to take advantage of the machine's computational power. The ASIC also includes a "flexible subsystem" based on eight programmable "geometry cores," each containing eight arithmetic pipelines. This talk will provide an overview of our work on parallel algorithms and machine architectures for high-speed MD simulation, with special attention to the respective roles of specialized vs. general-purpose hardware, and to the techniques used to minimize communication at various levels

关键词： Molecular dynamics

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Tight Competitive Ratios for parallel Disk Prefetching and Caching 08

Tight Competitive Ratios for Parallel Disk Prefetching and C...

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20th acm symposium on parallelism in algorithms and architectures

作者： Hon, Wing-Kai Shah, Rahul Varman, Peter J. Vitter, Jeffrey Scott Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Louisiana State Univ Dept Comp Sci Baton Rouge LA 70803 USA Rice Univ Dept ECE Houston TX 77251 USA Purdue Univ Coll Sci W Lafayette IN 47907 USA

ISBN: (纸本)9781595939739

We consider the natural extension of the well-known single disk caching problem to the parallel disk I/O model (PDM) [17]. The main challenge is to achieve as much parallelism as possible and avoid I/O bottlenecks. We are given a fast memory (cache) of size M memory blocks along with a request sequence Sigma = (b(1),b(2), ... ,b(n)) where each block b(i) resides on one of D disks. In each parallel I/O step, at most one block from each disk can be fetched. The task is to serve Sigma in the minimum number of parallel I/Os. Thus, each I/O is analogous to a page fault. The difference here is that during each page fault, up to D blocks can be brought into memory, as long as all of the new blocks entering the memory reside on different disks. The problem has a long history [18, 12, 13, 26]. Note that this problem is non-trivial even if all requests in Sigma are unique. This restricted version is called read-once. Despite the progress in the offline version [13, 15] and read-once version [12], the general online problem still remained open. Here, we provide comprehensive results with a full general solution for the problem with asymptotically tight competitive ratios. To exploit parallelism, any parallel disk algorithm needs a certain amount of lookahead into future requests. To provide effective caching, an online algorithm must achieve o(D) competitive ratio. We show a lower bound that states, for lookahead L <= M, any online algorithm must be Omega(D)-competitive. For lookahead L greater than M(1 + 1/epsilon), where c is a constant, the tight upper bound of O(root MD/L) on competitive ratio is achieved by our algorithm SKEW. The previous algorithm tLRU [26] was O((MD/L)(2/3)) competitive and this was also shown to be tight [26] for an LRU-based strategy. We achieve the tight ratio using a fairly different strategy than LRU. We also show tight results for randomized algorithms against oblivious adversary and give an algorithm achieving better bounds in the resource augme

关键词： Online algorithms Competitive Analysis parallel Disk Model

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Delaunay graphs of point sets in the plane with respect to axis-parallel rectangles

Delaunay graphs of point sets in the plane with respect to a...

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19th annual acm-SIAM symposium on Discrete algorithms

作者： Chen, Xiaomin Pach, János Szegedy, Mario Tardos, Gábor Google 76 Ninth Avenue New York NY 10011 United States City College CUNY and Courant Institute NYU 251 Mercer Street New York NY 10012 United States Rutgers University 110 Frelinghuysen Road Piscataway NJ 08854-8019 United States Simon Fraser University 8888 University Drive Burnaby BC V5A 1S6 Canada Rényi Institute Reáltanoda utca 13-15 H-1055 Budapest Hungary

ISBN: (纸本)9780898716474

Given a point set P in the plane, the Delaunay graph with respect to axis-parallel rectangles is a graph defined on the vertex set P, whose two points p,q ∈ P are connected by an edge if and only if there is a rectangle parallel to the coordinate axes that contains p and q, but no other elements of P. The following question of Even et al. [ELRS03] was motivated by a frequency assignment problem in cellular telephone networks. Does there exist a constant c > 0 such that the Delaunay graph of any set of n points in general position in the plane contains an independent set of size at least cn? We answer this question in the negative, by proving that the largest independent set in a randomly and uniformly selected point set in the unit square is O(n log 2 log n/log n), with probability tending to 1. We also show that our bound is not far from optimal, as the Delaunay graph of a uniform random set of n points almost surely has an independent set of size at least cn/log n. We give two further applications of our methods. 1. We construct 2-dimensional n-element partially ordered sets such that the size of the largest independent sets of vertices in their Hasse diagrams is o(n). This answers a question of Matoušek and Prívetivý [MaP06] and improves a result of Kríz and Nešetril [KrN91]. 2. For any positive integers c and d, we prove the existence of a planar point set with the property that no matter how we color its elements by c colors, we find an axis-parallel rectangle containing at least d points, all of which have the same color. This solves an old problem from [BrMP05].

关键词： Color

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Sparse parallel Delaunay Mesh Refinement 07

Sparse Parallel Delaunay Mesh Refinement

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19th annual symposium on parallelism in algorithms and architectures

作者： Hudson, Benoit Miller, Gary L. Phillips, Todd Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA

ISBN: (纸本)9781595936677

The authors recently introduced the technique of sparse mesh refinement to produce the first near-optimal sequential time bounds of O(n lg L/s+m) for inputs in any fixed dimension with piecewise-linear constraining (PLC) features. This paper extends that work to the parallel case, refining the same inputs in time O(lg(L/s)lg m) on an EREW PRAM while maintaining the work bound;in practice, this means we expect linear speedup for any practical number of processors. This is faster than the best previously known parallel Delaunay mesh refinement algorithms in two dimensions. It is the first technique with work bounds equal to the sequential case. In higher dimension, it is the first provably fast parallel technique for any kind of quality mesh refinement with PLC inputs. Furthermore, the algorithm's implementation is straightforward enough that it is likely to be extremely fast in practice.

关键词： Shared-Memory parallelism Mesh Generation Computational Geometry

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SuperMatrix Out-of-Order Scheduling of Matrix Operations for SMP and Multi-Core architectures 07

SuperMatrix Out-of-Order Scheduling of Matrix Operations for...

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19th annual symposium on parallelism in algorithms and architectures

作者： Chan, Ernie Quintana-Orti, Enrique S. Quintana-Orti, Gregorio van de Geijn, Robert Univ Texas Austin Dept Comp Sci Austin TX 78712 USA Univ Jaume 1 Dept Ingn & Ciencia Computad Castellon de La Plana Spain

ISBN: (纸本)9781595936677

We discuss the high-performance parallel implementation and execution of dense linear algebra matrix operations on SMP architectures;with an eye towards multi-core processors with many cores. We argue that traditional implementations, as those incorporated in LAPACK, cannot be easily modified to render high performance as well as scalability on these architectures. The solution we propose is to arrange the data structures and algorithms so that matrix blocks become the fundamental units of data;and operations on these blocks become the fundamental units of computation, resulting in algorithms-by-blocks as opposed to the snore traditional blocked algorithms. We show that this facilitates the adoption of techniques akin to dynamic scheduling and out-of-order execution usual in superscalar processors;which we name SuperMatrix Out-of-Order scheduling. Performance results on a 16 CPU Itanium2-based server are used to highlight opportunities and issues related to this new approach.

关键词： data affinity data-flow parallelism dense linear algebra libraries dynamic scheduling out-of-order execution

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A parallel Dynamic Programming Algorithm on a Multi-core Architecture 07

A Parallel Dynamic Programming Algorithm on a Multi-core Arc...

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19th annual symposium on parallelism in algorithms and architectures

作者： Tan, Guangming Sun, Ninghui Gao, Guang R. Chinese Acad Sci Key Lab Comp Syst & Architecture Beijing Peoples R China

ISBN: (纸本)9781595936677

Dynamic programming is an efficient technique to solve combinatorial search and optimization problem. There have been many parallel dynamic programming algorithms. The purpose of this paper is to study a family of dynamic programming algorithm where data dependence appear between non-consecutive stages, in other words, the data dependence is non-uniform. This kind of dynamic programming is typically called nonserial polyadic dynamic programming. Owing to the: non-uniform data dependence;it is harder to optimize this problem for parallelism and locality on parallel architectures. In this paper, we address the chanllenge of exploiting fine grain parallelism and locality of nonserial polyadic dynamic programming on a multi-core architecture. We present a programming and execution model for multi-core architectures with memory hierarchy. In the framework of the new model, the parallelism and locality benifit from a data dependence transformation. We propose a parallel pipelined algorithm for filling the dynamic programming matrix by decomposing the computation operators. The new parallel algorithm tolerates the memory access latency using multi-thread and is easily improved with the technique. We formulate and analytically solve the optimization problem determing the the size that minimizes the total execution time. The experiments on a simulator give a validation of the proposed model and show that the fine grain parallel algorithm achieves sub-linear speedup and that a potential high scalability on multi-core arichitecture.

关键词： Dynamic Programming Data Dependence Multicore Memory Hierarchy Scalabilitiy

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SPAA'07: proceedings of the Nineteenth annual symposium on parallelism in algorithms and architectures

SPAA'07: Proceedings of the Nineteenth Annual Symposium on P...

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SPAA'07: 19th annual symposium on parallelism in algorithms and architectures

ISBN: (纸本)159593667X

The proceedings contain 37 papers. The topics discussed include: on triangulation of simple networks;strong-diameter decompositions of minor free graphs;approximation algorithms for multiprocessor scheduling under uncertainty;scheduling DAGs on asynchronous processors;scheduling to minimize gaps and power consumption;cache-oblivious streaming B-trees;an experimental comparison of cache-oblivious and cache-conscious programs;scheduling threads for constructive cache sharing on CMPs;proximity-aware directory-based coherence for multi-core processor architectures;a parallel dynamic programming algorithm on a multi-core architecture;tight bounds for distributed selection;local MST computation with short advice;distributed approximation of capacitated dominating sets;packing to angles and sectors;and the notion of a timed register and its application to indulgent synchronization.

关键词： Computer programming

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Speed Scaling on parallel Processors 07

Speed Scaling on Parallel Processors

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19th annual symposium on parallelism in algorithms and architectures

作者： Albers, Susanne Mueller, Fabian Schmelzer, Swen Univ Freiburg Dept Comp Sci D-79110 Freiburg Germany

ISBN: (纸本)9781595936677

In this paper we investigate algorithmic instruments leading to low power consumption in computing devices. While previous work on energy-efficient algorithms has mostly focused on single processor environments, in this paper we investigate multi-processor settings. We study the basic problem of scheduling a set of jobs, each specified by a release time, a deadline and a processing volume, on variable speed processors so as to minimize the total energy consumption. We first settle the complexity of speed scaling with unit size jobs. More specifically, we devise a polynomial time algorithm for agreeable deadlines and prove NP-hardness results for arbitrary release dates and deadlines. For the latter setting we also develop a polynomial time algorithm achieving a constant factor approximation guarantee that is independent of the number of processors. Additionally, we study speed scaling of jobs with arbitrary processing requirements and, again, develop constant factor approximation algorithms. We finally transform our offline algorithms into constant competitive online strategies.

关键词： multiprocessor scheduling energy efficiency approximation algorithms online algorithms NP-completeness

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Proximity-Aware Directory-based Coherence for Multi-core Processor architectures 07

Proximity-Aware Directory-based Coherence for Multi-core Pro...

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19th annual symposium on parallelism in algorithms and architectures

作者： Brown, Jeffery A. Kumar, Rakesh Tullsen, Dean Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)9781595936677

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. This is exacerbated by the fact that interconnection speeds are not scaling well with technology. This paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores. These techniques exploit the differences in geometry between chip multiprocessors and traditional multiprocessor architectures. Directory-based protocols have been proposed as a scalable alternative to snoop-based protocols. In this paper, we discuss implementations of coherence for CMPs and propose and evaluate a novel directory-based coherence scheme to improve the performance of parallel programs on such processors. Proximity-aware coherence accelerates read and write misses by initiating cache-to-cache transfers from the spatially closest sharer. This has the dual benefit of eliminating unnecessary accesses to off-Chip memory, and minimizing the distance over which communicated data moves across the network. The proposed schemes result in speedups up to 74.9% for our workloads.

关键词： Chip Multiprocessors Coherence

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