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Beyond Nested parallelism: Tight Bounds on Work-Stealing Overheads for parallel Futures 09

Beyond Nested Parallelism: Tight Bounds on Work-Stealing Ove...

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21st acm symposium on parallelism in algorithms and architectures

作者： Spoonhower, Daniel Blelloch, Guy E. Gibbons, Phillip B. Harper, Robert Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781605586069

Work stealing is a popular method of scheduling fine-grained parallel tasks. The performance of work stealing has been extensively studied, both theoretically and empirically, but primarily for the restricted class of nested-parallel (or fully strict) computations. we extend this prior work by considering a broader class of programs that also supports pipelined parallelism through the use of parallel futures. Though the overhead of work-stealing schedulers is often quantified in terms of the number of steals, we show that a broader metric, the number of deviations, is a better way to quantify work-stealing overhead for less restrictive forms of parallelism, including parallel futures. For such parallelism, we prove bounds on work-stealing overheads-scheduler time and cache misses-as a function of the number of deviations Deviations can occur, for example, when work is stolen or when a future is touched. We also show instances where deviations can occur independently of steals and touches. Next, we prove that, under work stealing, the expected number of deviations is O(Pd+td) in a P-processor execution of a computation with span d and t touches of futures. Moreover, this bound is existentially tight for any work-stealing scheduler that is parsimonious (those where processors steal only when their queues are empty);this class includes all prior work-stealing schedulers. We also present empirical measurements of the number of deviations incurred by a classic application of futures, Halstead's quicksort, using our parallel implementation of ML. Finally, we identify a family of applications that use futures and, in contrast to quicksort, incur significantly smaller overheads.

关键词： scheduling work stealing futures performance bounds

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Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors

Thread Criticality Predictors for Dynamic Performance, Power...

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36th annual International symposium on Computer Architecture

作者： Bhattacharjee, Abhishek Martonosi, Margaret Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9781605585260

With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boil down to discerning which running threads or processes are critical, or slowest, versus which are non-critical If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. Possibilities include running the critical thread at a faster clock rate, performing load balancing techniques to offload work onto currently non-critical threads, or giving the critical thread more on-chip resources to execute faster. This paper proposes and evaluates simple but effective thread criticality predictors for parallel applications. We show that accurate predictors can be built using counters that are typically already available on-chip. Our predictor, based on memory hierarchy statistics, identifies thread criticality with an average accuracy of 93% across a range of architectures. We also demonstrate two applications of our predictor. First, we show how Intel's Threading Building Blocks (TBB) parallel runtime system can benefit from task stealing techniques that use our criticality predictor to reduce load imbalance. Using criticality prediction to guide TBB's task-stealing decisions improves performance by 13-32% for TBB-based PARSEC benchmarks running on a 32-core CMP. As a second application, criticality prediction guides dynamic energy optimizations in barrier-based applications. By running the predicted critical thread at the full clock rate and frequency-scaling non-critical threads, this approach achieves average energy savings of 15% while negligibly degrading performance for SPLASH-2 and PARSEC benchmarks.

关键词： Thread Criticality Prediction parallel Processing Intel TBB DVFS Caches

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Brief Announcement: Optimal Speedup on a Low-Degree Multi-Core parallel Architecture (LoPRAM)

Brief Announcement: Optimal Speedup on a Low-Degree Multi-Co...

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20th acm symposium on parallelism in algorithms and architectures

作者： Dorrigiv, Reza Lopez-Ortiz, Alejandro Salinger, Alejandro Univ Waterloo Sch Comp Sci Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781595939739

Over the last five years, major microprocessor manufacturers have released plans for a rapidly increasing number of cores per microprossesor, with upwards of 64 cores by 2015. In this setting, a sequential RAM computer will no longer accurately reflect the architecture on which algorithms are being executed. In this paper we propose a model of low degree parallelism (LoPRAM) which builds upon the RAM and PRAM models yet better reflects recent advances in parallel (multi-core) architectures. This model supports a high level of abstraction that simplifies the design and analysis of parallel programs. More importantly we show that in many instances it naturally leads to work-optimal parallel algorithms via simple modifications to sequential algorithms.

关键词： algorithms Theory

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Fundamental parallel algorithms for Private-Cache Chip Multiprocessors 08

Fundamental Parallel Algorithms for Private-Cache Chip Multi...

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20th acm symposium on parallelism in algorithms and architectures

作者： Arge, Lars Goodrich, Michael T. Nelson, Michael Sitchinava, Nodari Univ Aarhus MADALGO Aarhus Denmark Univ Calif Irvine Irvine CA 92697 USA

ISBN: (纸本)9781595939739

In this paper, we study parallel algorithms for private-cache chip multiprocessors (CMPs), focusing on methods for foundational problems that are scalable with the number of cores. By focusing on private-cache CMPs, we show that we can design efficient algorithms that need no additional assumptions about the way cores are interconnected, for we assume that all inter-processor communication occurs through the memory hierarchy. We study several fundamental problems, including prefix sums, selection, and sorting, which often form the building blocks of other parallel algorithms. Indeed, we present two sorting algorithms, a distribution sort and a mergesort. Our algorithms are asymptotically optimal in terms of parallel cache accesses and space complexity under reasonable assumptions about the relationships between the number of processors, the size of memory, and the size of cache blocks. In addition, we study sorting lower bounds in a computational model, which we call the parallel external-memory (PEM) model, that formalizes the essential properties of our algorithms for private-cache CMPs.

关键词： parallel External Memory PEM private-cache CMP

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Directed Transmission Method, a Fully Asynchronous Approach to Solve Sparse Linear Systems in parallel 08

Directed Transmission Method, a Fully Asynchronous Approach ...

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20th acm symposium on parallelism in algorithms and architectures

作者： Wei, Fei Yang, Huazhong Tsinghua Univ Dept Elect Engn Beijing Peoples R China

ISBN: (纸本)9781595939739

There are many algorithms to solve large sparse linear systems in parallel;however, most of them acquire synchronization and thus are lack of scalability. In this paper, we propose a new distributed numerical algorithm, called Directed Transmission Method (DTM). DTM is a fully asynchronous, scalable and continuous-time iterative algorithm to solve the arbitrarily-large sparse linear system whose coefficient matrix is symmetric-positive-definite (SPD). DTM is able to be freely running on the heterogeneous parallel computer with arbitrary number of processors, which might be manycore microprocessors, clusters, grids, clouds, and the Internet. We proved that DTM is convergent by making use of the final value theorem of Laplacian Transformation. Numerical experiments show that DTM is efficient.

关键词： Asynchronous Algorithm Convergence Theory Directed Transmission Method (DTM) Distributed Algorithm Sparse Linear System Virtual Transmission Method (VTM)

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Finding Strongly Connected Components in parallel using O(log² n) Reachability Queries 08

Finding Strongly Connected Components in Parallel using <i>O...

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20th acm symposium on parallelism in algorithms and architectures

作者： Schudy, Warren Brown Univ Providence RI 02912 USA

ISBN: (纸本)9781595939739

We give a randomized (Las-Vegas) parallel algorithm for computing strongly connected components of a graph with n vertices and m edges. The runtime is dominated by O(log(2) n) multi-source parallel reachability queries;i.e. O(log(2) n) calls to a subroutine that computes the union of the descendants of a given set of vertices in a given digraph. Our algorithm also topologically sorts the strongly connected components. Using Ullman and Yannakakis's [22] techniques for the reachability subroutine gives our algorithm runtime (O) over tilde (t) using mn/t(2) processors for any (n(2)/m)(1/3) <= t <= n. On sparse graphs, this improves the number of processors needed to compute strongly connected components and topological sort within time n(1/3) <= t <= n from the previously best known (n/t)(3) [20] to (n/t)(2).

关键词： Graph algorithms parallel algorithms Strongly connected components Topological sort Transitive closure bottleneck

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DREADLOCKS: Efficient Deadlock Detection 08

DREADLOCKS: Efficient Deadlock Detection

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20th acm symposium on parallelism in algorithms and architectures

作者： Koskinen, Eric Herlihy, Maurice Brown Univ Dept Comp Sci Providence RI 02912 USA

ISBN: (纸本)9781595939739

We present Dreadlocks. an efficient new shared-memory spin lock that actively detects deadlocks. Instead of spinning on a Boolean value, each thread spins on the lock owner's per-thread digest, a compact representation of a portion of the lock's waits-for graph. Digests can be implemented either as bit vectors (for small numbers of threads) or as Bloom filters (for larger numbers of threads). Updates to digests are propagated dynamically as locks are acquired and released. Dreadlocks can be applied to any spin lock algorithm that allows threads to time out. Experimental results show that Dreadlocks outperform timeouts under many circumstances, and almost never do worse.

关键词： Concurrency parallel programming deadlock deadlock detection bloom filters transactional memory

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Checkpoints and Continuations Instead of Nested Transactions 08

Checkpoints and Continuations Instead of Nested Transactions

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20th acm symposium on parallelism in algorithms and architectures

作者： Koskinen, Eric Herlihy, Maurice Brown Univ Dept Comp Sci Providence RI 02912 USA

ISBN: (纸本)9781595939739

We present a mechanism for partially aborting transactions through the use of data structure checkpoints and control-flow continuations. In particular, we show that boosted transactions [9] already have built-in restoration points and afford a simple, efficient implementation. Our mechanism is far simpler than previous work, which relied on complex nesting schemes to establish checkpoints. We demonstrate syntactic advantages and we quantify the overhead of checkpoints and explore several examples, illustrating the utility of partially aborting transactions. We additionally present a novel queue-based spin lock which allows threads to timeout and differ in priority. Unlike the known lock due to Craig [5], our lock is more efficient for priority schemes of few levels.

关键词： Concurrency parallel programming transactional memory boosting checkpoints continuations

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parallelizing Dynamic Information Flow Tracking 08

Parallelizing Dynamic Information Flow Tracking

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20th acm symposium on parallelism in algorithms and architectures

作者： Ruwase, Olatunji Gibbons, Phillip B. Mowry, Todd C. Ramachandran, Vijaya Chen, Shimin Kozuch, Michael Ryan, Michael Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781595939739

Dynamic information flow tracking (DIFT) is an important tool for detecting common security attacks and memory bugs. A DIFT tool tracks the flow of information through a monitored program's registers and memory locations as the program executes, detecting and containing/fixing problems on-the-fly. Unfortunately, sequential DIFT tools are quite slow, and DIFT is quite challenging to parallelize. In this paper, we present a new approach to parallelizing DIFT-like functionality. Extending our recent work on accelerating sequential DIFT, we consider a variant of DIFT that tracks the information flow only through unary operations (relaxed DIFT), and yet makes sense for detecting security attacks and memory bugs. We present a parallel algorithm for relaxed DIFT, based on symbolic inheritance tracking, which achieves linear speed-up asymptotically. Moreover, we describe techniques for reducing the constant factors, so that speed-ups can be obtained even with just a few processors. We implemented the algorithm in the context of a Log-Based architectures (LBA) system, which provides hardware support for logging a program trace and delivering it to other (monitoring) processors. Our simulation results on SPEC benchmarks and a video player show that our parallel relaxed DIFT reduces the overhead to as low as 1.2X using 9 monitoring cores on a 16-core chip multiprocessor.

关键词： dynamic information flow tracking (DIFT) program monitoring log-based monitoring parallel algorithm taint analysis

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On the Performance of parallel Neural Network Implementations on Distributed Memory architectures 08

On the Performance of Parallel Neural Network Implementation...

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8th IEEE International symposium on Cluster Computing and the Grid

作者： Ganeshamoorthy, K. Ranasinghe, D. N. Univ Colombo Sch Comp Dept Computat & Intelligent Syst Colombo 07 Sri Lanka

ISBN: (纸本)9781424442379

In this paper, we study the impact of multi processor memory systems in particular, the distributed memory (I)M) and virtual shared memory (VSM), on the implementation of parallel backpropagation neural network algorithms. In the first instance, neural network is partitioned into sub neural networks by applying a hybrid partitioning scheme. In the second, each partitioned network is evaluated with matrix multiplication. Three different sizes of neural networks are used and exchange rate prediction used as a reference problem. parallel implementations for each of the distributed memory and virtual shared memory scenarios is obtained. These algorithms are implemented on a high performance cluster, "Monolith" consisting of over 396 nodes. Programming is realized using Message Passing Interface (MPI) library and C-Linda. The partitioned, matrix multiplication has the fastest execution time, and DM/MPI implementation is always faster than the VSM/Linda equivalent. However in VSM/Linda it is possible to allow the parallel neural network to choose the optimum number of processors dynamically.

关键词： VSM DM Hybrid partition parallel neural network

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