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Can a shared-memory model serve as a bridging model for parallel computation?

Can a shared-memory model serve as a bridging model for para...

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Gibbons, Phillip B. Matias, Yossi Ramachandran, Vijaya Lucent Technologies Murray Hill United States

We consider the question of whether a shared-memory model can serve as an effective bridging model for parallel computation along the lines of a distributed-memory model such as the BSP. As a candidate for a shared-memory bridging model, we introduce the Queuing Shared Memory (QSM) model, which accounts for limited communication bandwidth while still providing a simple shared-memory abstraction. We substantiate the ability of the QSM to serve as a bridging model by providing a simple work-preserving emulation of the QSM on both the BSP, and on a related model, the (d,x)-BSP. We present evidence that the features of the QSM are essential to its effectiveness as a bridging model. In addition, we describe scenarios in which the high-level QSM is more suited for analyzing algorithms on certain machines than the more detailed BSP and LogP models. Finally, we present algorithmic results for the QSM, as well as general strategies for mapping algorithms designed for the BSP or PRAM models onto the QSM model. Our main conclusion is that shared-memory models can potentially serve as viable alternatives to existing message-passing, distributed-memory bridging models.

关键词： parallel processing systems

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Using tadpoles to reduce memory and communication requirements for exhaustive, breadth-first search using distributed computers 97

Using tadpoles to reduce memory and communication requiremen...

引用

proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Cooperman, Gene Tselman, Michael Northeastern Univ Boston MA United States

ISBN: (纸本)9780897918909

A parallel variant of breadth-first search for distributed computing is presented. The variant allows exhaustive enumeration of elements of a search space (implicitly defined graph) in which the representation of all graph nodes would otherwise require more than the total available memory. This algorithm requires the use of a tadpole data structure to partition the search space into connected subgraphs, with each subgraph stored within the memory of a single processor. Thus, the graph of the nodes are stored in a way that adds greater spatial locality, thereby reducing communication among processors. The algorithm enumerates the tadpoles in a breadth-first manner while executing depth-first search within each tadpole. The search within each tadpole is reduced to tree search. A parameter is defined that allows a linear tradeoff in which memory and communication are each reduced linearly as CPU time grows. The result appears to fill a gap in the literature, which has concentrated on parallel depth-first search, but has been relatively sparse in the case of parallel breadth-first search.

关键词： parallel processing systems

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From algorithm parallelism to instruction-level parallelism: An encode-decode chain using prefix-sum

From algorithm parallelism to instruction-level parallelism:...

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Vishkin, Uzi

A novel comprehensive and coherent approach for the purpose of increasing instruction-level parallelism (ILP) is devised. The key new tool in our envisioned system update is the addition of a parallel prefix-sum (PS) instruction, which will have efficient implementation in hardware, to the instruction-set architecture. This addition gives for the first time a concrete way for recruiting the whole knowledge base of parallel algorithms for that purpose. The potential increase in ILP is demonstrated by experimental results for a test application. The main technical contribution is in the form of a `completeness theorem'. Perhaps surprisingly, the current abstract proves that in an envisioned system which employs parallel PS functional units, a proper use of a serial programming language suffices for the following. With a moderate effort, one can program a parallel algorithm (in a serial language), so that a parallelizing compiler (even without run-time methods!) will be able to extract the same (i.e., `complete') ILP from such serial code as from code written in a parallel language. Alternatively, rather than have the programmer produce the serial code, a precompiler could derive it from a parallel language. The most interesting idea in the proof is the reliance on the new parallel PS for circumventing collision-ambiguity in references to memory. Other new ideas in the paper include hardware-design of a prefix-sum unit and an on-line algorithm for high-bandwidth register-files. An informal upshot of this paper is the following general insight: to accommodate parallelism in uniprocessor systems (from algorithms to ILP), it is sufficient to only add (and, of course, incorporate) parallel prefix-sum functional units to standard serial system designs.

关键词： parallel algorithms

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Approximation algorithms for structured communication problems 97

Approximation algorithms for structured communication proble...

引用

proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Barth, Dominique Fraigniaud, Pierre Universite de Paris Sud - CNRS Orsay France

ISBN: (纸本)9780897918909

Given a network of processors, a structured communication problem consists to route a communication pattern known in advance. Structured communication problems appear frequently in parallel computing. Hence, communication libraries (e.g, PVM or MPI) generally include a specific access to procedures solving the most common problems of this type. A standard communication model assumes that information proceeds by a sequence of calls between neighboring nodes of the network, and that each node is allowed to call at most one neighbor at a time. In this context, most of the decision problems corresponding to the usual structured communication problems have been shown to be NP-complete. Therefore, several approximation algorithms have been proposed to solve specific problems. Each of these algorithms is dedicated to a particular problem. In this paper, we present a high level method which can be used to derive approximation algorithms for many different structured communication problems on arbitrary networks. This method is shown to be quite efficient. For instance, in the case of broadcasting (one-to-all) and gossiping (all-to-all), it allows to obtain algorithms which approach, and even sometime achieve, the performances of the best known algorithms which were designed using specific techniques defined in purpose for each problem. Moreover, in the case of scattering (personalized one-to-all) and multi-scattering (personalized all-to-all), our method allows to obtain optimal results. Our method is based on the simulation on arbitrary networks of movements of data induced by communication algorithms derived for specific architectures and/or specific communication models. This simulation uses sophisticated embedding and scheduling techniques.

关键词： parallel algorithms

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HARP: A fast spectral partitioner

HARP: A fast spectral partitioner

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Simon, Horst D. Sohn, Andrew Biswas, Rupak Lawrence Berkeley Natl Lab Berkeley United States

Partitioning unstructured graphs is central to the parallel solution of computational science and engineering problems. Spectral partitioners, such recursive spectral bisection (RSB), have proven effective in generating high-quality partitions of realistically-sized meshes. The major problem which hindered their widespread use was their long execution times. This paper presents a new inertial spectral partitioner, called HARP. The main objective of the proposed approach is to quickly partition the meshes at runtime in a manner that works efficiently for real applications in the context of distributed-memory machines. The underlying principle of HARP is to find the eigenvectors of the unpartitioned vertices and then project them onto the eigenvectors of the original mesh. Results for various meshes ranging in size from 1000 to 100,000 vertices indicate that HARP can indeed partition meshes rapidly at runtime. Experimental results show that our largest mesh can be partitioned sequentially in only a few seconds on an SP2 which is several times faster than other spectral partitioners while maintaining the solution quality of the proven RSB method. A parallel MPI version of HARP has also been implemented on IBM SP2 and Cray T3E. parallel HARP, running on 64 processors SP2 and T3E, can partition a mesh containing more than 100,000 vertices into 64 subgrids in about half a second. These results indicate that graph partitioning can now be truly embedded in dynamically-changing real-world applications.

关键词： parallel processing systems

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Fine-grain multithreading with the EM-X multiprocessor 97

Fine-grain multithreading with the EM-X multiprocessor

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Sohn, Andrew Kodama, Yuetsu Ku, Jui Sato, Mitsuhisa Sakane, Hirofumi Yamana, Hayato Sakai, Shuichi Yamaguchi, Yoshinori New Jersey Inst of Technology Newark NJ United States

ISBN: (纸本)9780897918909

Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multiprocessor through empirical studies. The EM-X provides hardware supports for fine-grain multithreading, including a by-passing mechanism for direct remote reads and writes, hardware FIFO thread scheduling, and dedicated instructions for generating fixed-sized communication packets. Bitonic sorting and Fast Fourier Transform are selected for experiments. Parameters that characterize the performance of multithreading are investigated, including the number of threads, the number of thread switches, the run length, and the number of remote reads. Experimental results indicate that the best communication performance occurs when the number of threads is two to four. FFT yielded over 95% overlapping due to a large amount of computation and communication parallelism across threads. Even in the absence of thread computation parallelism, multithreading helps overlap over 35% of the communication time for bitonic sorting.

关键词： parallel processing systems

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Localized algorithm for parallel association mining

Localized algorithm for parallel association mining

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Zaki, Mohammed Javeed Parthasarathy, Srinivasan Li, Wei Univ of Rochester Rochester United States

Discovery of association rules is an important database mining problem. Mining for association rules involves extracting patterns from large databases and inferring useful rules from them. Several parallel and sequential algorithms have been proposed in the literature to solve this problem. Almost all of these algorithms make repeated passes over the database to determine the commonly occurring patterns or itemsets (set of items), thus incurring high I/O overhead. In the parallel case, these algorithms do a reduction at the end of each pass to construct the global patterns, thus incurring high synchronization cost. In this paper we describe a new parallel association mining algorithm. Our algorithm is a result of detailed study of the available parallelism and the properties of associations. The algorithm uses a scheme to cluster related frequent itemsets together, and to partition them among the processors. At the same time it also uses a different database layout which clusters related transactions together, and selectively replicates the database so that the portion of the database needed for the computation of associations is local to each processor. After the initial set-up phase, the algorithm eliminates the need for further communication or synchronization. The algorithm further scans the local database partition only three times, thus minimizing I/O overheads. Unlike previous approaches, the algorithms uses simple intersection operations to compute frequent itemsets and doesn't have to maintain or search complex hash structures. Our experimental testbed is a 32-processor DEC Alpha cluster inter-connected by the Memory Channel network. We present results on the performance of our algorithm on various databases, and compare it against a well known parallel algorithm. Our algorithm outperforms it by an more than an order of magnitude.

关键词： parallel algorithms

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Memory hierarchy design for jetpipeline: To execute scalar and vector instructions in parallel

Memory hierarchy design for jetpipeline: To execute scalar a...

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2nd AIZU International symposium on parallel algorithms/Architecture Synthesis

作者： Sasaki, T Nakaike, T Takano, K Katahira, M Kobayashi, H Nakamura, T Tohoku Univ Sendai-shi Japan

ISBN: (纸本)0818678704

Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, this paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.

关键词： parallel processing systems

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Space-efficient scheduling of parallelism with synchronization variables 97

Space-efficient scheduling of parallelism with synchronizati...

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Blelloch, Guy E. Gibbons, Phillip B. Matias, Yossi Narlikar, Girija J. Carnegie Mellon Pittsburgh PA United States

ISBN: (纸本)9780897918909

Recent work on scheduling algorithms has resulted in provable bounds on the space taken by parallel computations in relation to the space taken by sequential computations. The results for online versions of these algorithms, however, have been limited to computations in which threads can only synchronize with ancestor or sibling threads. Such computations do not include languages with futures or user-specified synchronization constraints. Here we extend the results to languages with synchronization variables. Such languages include languages with futures, such as Multilisp and Cool, as well as other languages such as ID. The main result is an online scheduling algorithm which, given a computation with w work (total operations), σ synchronizations, d depth (critical path) and s1 sequential space, will run in O(w/p+σlog(pd)/p+d log(pd)) time and s1+O(pd log (pd)) space, on a p-processor CRCW PRAM with a fetch-and-add primitive. This includes all time and space costs for both the computation and the scheduler. The scheduler is non-preemptive in the sense that it will only move a thread if the thread suspends on a synchronization, forks a new thread, or exceeds a threshold when allocating space. For the special case where the computation is a planar graph with left-to-right synchronization edges, the scheduling algorithm can be implemented in O(w/p+d log p) time and s1+O(pd log p) space. These are the first non-trivial space bounds described for such languages.

关键词： parallel algorithms

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Efficient computations on fault-prone BSP machines 97

Efficient computations on fault-prone BSP machines

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proceedings of the 1997 9th annual acm symposium on parallel algorithms and architectures, SPAA

作者： Kontogiannis, Spyros C. Pantzio, Grammati E. Spirakis, Paul G. Patras Univ Patras Greece

ISBN: (纸本)9780897918909

In this paper general simulations of algorithms designed for fully operational BSP machines on BSP machines with faulty or unavailable processors, are developed. The fail-stop model is considered for the fault occurrences, that is, if a processor fails or becomes unavailable, it remains so until the end of the computation. The faults are random, in the sense that a processor may fail independently with probability at most a, where a is a constant. Two possible settings for fault occurrences are considered: the static case where the faults are static (the faulty or unavailable processors are already known at the beginning of the computation), and the dynamic case where the processors may become faulty or unavailable during the computation. In the case of static faults, a simulation of an n-processor fault-free BSP machine on a faulty n-processor BSP machine is presented with constant slowdown per local computation step and O(log n·max{L, g}) slowdown per communication step, given that a preprocessing has been done that needs O(n/log n·max{L, g}) time (L and g are the parameters of the simulating BSP machine). In the case of dynamic faults, a simulation of an n-processor fault-free BSP machine on an cn·log n-processor faulty BSP machine is presented. No dynamic faults may occur during certain periods of the simulation. The simulations are randomized and Monte Carlo: they are guaranteed to be correct with high probability, and the time bounds always hold. To our knowledge, no previous work on the fault tolerance of the BSP model exists.

关键词： parallel processing systems

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