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proceedings of the annual International symposium on Microarchitecture, MICRO

Proceedings of the Annual International Symposium on Microar...

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47th annual IEEE/acm International symposium on Microarchitecture, MICRO 2014

The proceedings contain 53 papers. The topics discussed include: transparent hardware management of stacked DRAM as part of memory;unison cache: a scalable and effective die-stacked DRAM cache;locality-aware mapping of nested parallel patterns on GPUs;accelerating irregular algorithms on GPGPUs using fine-grain hardware worklists;exploring the design space of SPMD divergence management on data-parallel architectures;managing GPU concurrency in heterogeneous architectures;FIRM: fair and high-performance memory control for persistent memory systems;efficient memory virtualization: reducing dimensionality of nested page walks;Iso-X: a flexible architecture for hardware-managed isolated execution;cc-hunter: uncovering covert timing channels on shared processor hardware;a practical methodology for measuring the side-channel signal available to the attacker for instruction-level events;and calculating architectural vulnerability factors for spatial multi-bit transient faults.

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Exploring the Design Space of SPMD Divergence Management on Data-parallel architectures 47

Exploring the Design Space of SPMD Divergence Management on ...

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47th annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Lee, Yunsup Grover, Vinod Krashinsky, Ronny Stephenson, Mark Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781479969982

Data-parallel architectures must provide efficient support for complex control-flow constructs to support sophisticated applications coded in modern single-program multiple-data languages. As these architectures have wide datapaths that process a single instruction across parallel threads, a mechanism is needed to track and sequence threads as they traverse potentially divergent control paths through the program. The design space for divergence management ranges from software-only approaches where divergence is explicitly managed by the compiler, to hardware solutions where divergence is managed implicitly by the microarchitecture. In this paper, we explore this space and propose a new predication-based approach for handling control-flow structures in data-parallel architectures. Unlike prior predication algorithms, our new compiler analyses and hardware instructions consider the commonality of predication conditions across threads to improve efficiency. We prototype our algorithms in a production compiler and evaluate the tradeoffs between software and hardware divergence management on current GPU silicon. We show that our compiler algorithms make a predication-only architecture competitive in performance to one with hardware support for tracking divergence.

关键词： Vectors Hardware Computer architecture Registers Optimization Software Support vector machines

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SPAA 2014 - proceedings of the 26th acm symposium on parallelism in algorithms and architectures

SPAA 2014 - Proceedings of the 26th ACM Symposium on Paralle...

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26th acm symposium on parallelism in algorithms and architectures, SPAA 2014

ISBN: (纸本)9781450328210

The proceedings contain 42 papers. The topics discussed include: on dynamic bin packing for resource allocation in the cloud;on the online fault-tolerant server consolidation problem;on computing maximal independent sets of hypergraphs in parallel;simple parallel and distributed algorithms for spectral graph sparsification;concurrent data structures for efficient streaming aggregation;provably good scheduling for parallel programs that use data structures through implicit batching;scheduling selfish jobs on multidimensional parallel machines;LP rounding and combinatorial algorithms for minimizing active and busy time;a note on multiprocessor speed scaling with precedence constraints;executing dynamic data-graph computations deterministically using chromatic scheduling;the PCL theorem. transactions cannot be parallel, consistent and live;adaptive integration of hardware and software lock elision techniques;and transaction-friendly condition variables.

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Managing GPU Concurrency in Heterogeneous architectures 47

Managing GPU Concurrency in Heterogeneous Architectures

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47th annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Kayiran, Onur Nachiappan, Nachiappan Chidambaram Jog, Adwait Ausavarungnirun, Rachata Kandemir, Mahmut T. Loh, Gabriel H. Mutlu, Onur Das, Chita R. Penn State Univ University Pk PA 16802 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Adv Micro Devices Inc Sunnyvale CA 94088 USA

ISBN: (纸本)9781479969982

Heterogeneous architectures consisting of general-purpose CPUs and throughput-optimized GPUs are projected to be the dominant computing platforms for many classes of applications. The design of such systems is more complex than that of homogeneous architectures because maximizing resource utilization while minimizing shared resource interference between CPU and GPU applications is difficult. We show that GPU applications tend to monopolize the shared hardware resources, such as memory and network, because of their high thread-level parallelism (TLP), and discuss the limitations of existing GPU-based concurrency management techniques when employed in heterogeneous systems. To solve this problem, we propose an integrated concurrency management strategy that modulates the TLP in GPUs to control the performance of both CPU and GPU applications. This mechanism considers both GPU core state and system-wide memory and network congestion information to dynamically decide on the level of GPU concurrency to maximize system performance. We propose and evaluate two schemes: one (CM-CPU) for boosting CPU performance in the presence of GPU interference, the other (CM-BAL) for improving both CPU and GPU performance in a balanced manner and thus overall system performance. Our evaluations show that the first scheme improves average CPU performance by 24%, while reducing average GPU performance by 11%. The second scheme provides 7% average performance improvement for both CPU and GPU applications. We also show that our solution allows the user to control performance trade-offs between CPUs and GPUs.

关键词： concurrency control graphics processing units multi-threading parallel architectures performance evaluation resource allocation CM-BAL CM-CPU CPU performance GPU core state GPU interference GPU performance GPU-based concurrency management techniques TLP general-purpose CPU heterogeneous architectures heterogeneous systems homogeneous architectures integrated concurrency management strategy network congestion information resource utilization shared hardware resources shared resource interference minimization system-wide memory thread-level parallelism throughput-optimized GPU Bandwidth Central Processing Unit Computer architecture Concurrent computing Graphics processing units Resource management System performance CPU-GPU GPUs concurrency resource management scheduling central processing units Graphics Processing Unit Resource utilization management of resources GRAPPER PICK UP System performance Concurrency HETEROGENEOUS SYSTEM Multithreading hardware resource Concurrency control parallel architectures Computer Architecture parallel programming Bandwidth

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Efficient dynamic scheduling of heterogeneous applications in hybrid architectures 14

Efficient dynamic scheduling of heterogeneous applications i...

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29th annual acm symposium on Applied Computing, SAC 2014

作者： Andrade, Guilherme Ramos, Gabriel Madeira, Daniel Sachetto, Rafael Clua, Esteban Ferreira, Renato Rocha, Leonardo Universidade Federal de São João Del Rey Computer Science São João Del Rei Brazil Universidade Federal de Minas Gerais Computer Science Belo Horizonte Brazil Universidade Federal Fluminense Computer Science Niterói Brazil

ISBN: (纸本)9781450324694

The emergence of different applications that deal with growing amounts of data at reasonable times, has stimulated the development of new computing architectures consisting of different processing units (PU). Runtime environments have been proposed in order to exploit these resource as much as possible by offering a variety of methods for dynamically scheduling tasks on different PUs. These schedulers determine which PU is better suited for executing each task, based upon a set of task parameters such as the amount of data, computation requirements, etc. Although large number of applications are heterogeneous, composed of tasks with different characteristics, the current techniques focus on these characteristics as isolated features leading to inefficient executions in several situations. In this work we present two new scheduling strategies, combining different existing strategies, that leads to more efficient executions in different scenarios. Our results show that our approach can be up to 20% more efficient than current techniques. Copyright 2014 acm.

关键词： parallel algorithms

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

The proceedings contain 39 papers. The topics discussed include: Fast greedy algorithms in MapReduce and streaming;reduced hardware transactions: a new approach to hybrid transactional memory;recursive design of hardware priority queues;drop the anchor: lightweight memory management for non-blocking data structures;scalable statistics counters;storage and search in dynamic peer-to-peer networks;expected sum and maximum of displacement of random sensors for coverage of a domain;on dynamics in selfish network creation;brief announcement: truly parallel burrows-wheeler compression and decompression;brief announcement: locality in wireless scheduling;brief announcement: universally truthful secondary spectrum auctions;and brief announcement: online batch scheduling for flow objectives.

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Distributed algorithms for barrier coverage using relocatable sensors 13

Distributed algorithms for barrier coverage using relocatabl...

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2013 acm symposium on Principles of Distributed Computing, PODC 2013

作者： Eftekhari, Mohsen Kranakis, Evangelos Krizanc, Danny Morales-Ponce, Oscar Narayanan, Lata Opatrny, Jaroslav Dept. Comp. Sci. and Soft. Eng. Concordia University Montreal Canada School of Comp. Sci. Carleton University Ottawa Canada Dept. of Math. and Comp. Sci. Wesleyan University Middletown United States Dept. of Comp. Science Chalmers U. of Tech. Gothenburg Sweden

ISBN: (纸本)9781450320658

We study the barrier coverage problem using relocatable sensor nodes. We assume each sensor can sense an intruder or event inside its sensing range. Sensors are initially located at arbitrary positions on the barrier and can move along the barrier. The goal is to find final positions for sensors so that the entire barrier is covered. In recent years, the problem has been studied extensively in the centralized setting. In this paper, we study the problem in the distributed setting. We assume each sensor repeatedly executes a Look-Compute-Move cycle: based on what it sees in its vicinity, it makes a decision on where to move, and moves to its next position. We make two strong but realistic restrictions on the capabilities of sensors: they have a constant visibility rang e and can move only a constant distance in every cycle. In this model, we give the first two distributed algorithms that achieve barrier coverage for a line segment barrier when there are enough nodes in the network to cover the entire barrier. Our algorithms are synchronous, and local in the sense that sensors make their decisions independently based only on what they see within their constant visibility range. One of our algorithms is oblivious whereas the other uses two bits of memory at each sensor to store the type of move made in the previous step. We show that our oblivious algorithm terminates within θ(n2) steps with the barrier fully covered, while the constant-memory algorithm is shown to take θ(n) steps to terminate in the worst case. Since any algorithm that can only move a constant distance in one step requires ω(n) steps on some inputs, our second algorithm is asymptotically optimal. Finally, both our algorithms are self-stabilizing, and can be easily extended to the case of non-homogeneous sensors, and for the case when the barrier is a circle. Copyright 2013 acm.

关键词： parallel algorithms

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Drop the Anchor: Lightweight Memory Management for Non-Blocking Data Structures 13

Drop the Anchor: Lightweight Memory Management for Non-Block...

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annual acm symposium on parallel algorithms and architectures

作者： Anastasia Braginsky Alex Kogan Erez Petrank Computer Science Technion Oracle Labs

ISBN: (纸本)9781450315722

Efficient memory management of dynamic non-blocking data structures remains an important open question. Existing methods either sacrifice the ability to deallocate objects or reduce performance notably. In this paper, we present a novel technique, called Drop the Anchor, which significantly reduces the overhead associated with the memory management while reclaiming objects even in the presence of thread failures. We demonstrate this memory management scheme on the common linked list data structure. Using extensive evaluation, we show that Drop the Anchor significantly outperforms Hazard Pointers, the widely used technique for non-blocking memory management.

关键词： Concurrent data structures progress guarantee lock-freedom parallel programming linked list memory management hazard pointers timestamps freezing

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Locality-Aware Task Management for Unstructured parallelism: A Quantitative Limit Study 13

Locality-Aware Task Management for Unstructured Parallelism:...

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annual acm symposium on parallel algorithms and architectures

作者： Richard M. Yoo Christopher J. Hughes Changkyu Kim Yen-Kuang Chen Christos Kozyrakis Parallel Computing Laboratory Intel Labs Santa Clara CA 95054 Pervasive Parallelism Laboratory Stanford University Stanford CA 94305

ISBN: (纸本)9781450315722

As we increase the number of cores on a processor die, the on-chip cache hierarchies that support these cores are getting larger, deeper, and more complex. As a result, non-uniform memory access effects are now prevalent even on a single chip. To reduce execution time and energy consumption, data access locality should be exploited. This is especially important for task-based programming systems, where a scheduler decides when and where on the chip the code segments, i.e., tasks, should execute. Capturing locality for structured task parallelism has been done effectively, but the more difficult case, unstructured parallelism, remains largely unsolved-little quantitative analysis exists to demonstrate the potential of locality-aware scheduling, and to guide future scheduler implementations in the most fruitful direction. This paper quantifies the potential of locality-aware scheduling for unstructured parallelism on three different many-core processors. Our simulation results of 32-core systems show that locality-aware scheduling can bring up to 2.39x speedup over a randomized schedule, and 2.05x speedup over a state-of-the-art baseline scheduling scheme. At the same time, a locality-aware schedule reduces average energy consumption by 55% and 47%, relative to the random and the baseline schedule, respectively. In addition, our 1024-core simulation results project that these benefits will only increase: Compared to 32-core executions, we see up to 1.83x additional locality benefits. To capture such potentials in a practical setting, we also perform a detailed scheduler design space exploration to quantify the impact of different scheduling decisions. We also highlight the importance of locality-aware stealing, and demonstrate that a stealing scheme can exploit significant locality while performing load balancing. Over randomized stealing, our proposed scheme shows up to 2.0x speedup for stolen tasks.

关键词： Task Scheduling Task Stealing Locality Performance Energy

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Truly parallel burrows-wheeler compression and decompression 13

Truly parallel burrows-wheeler compression and decompression

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proceedings of the twenty-fifth annual acm symposium on parallelism in algorithms and architectures

作者： James Alexander Edwards Uzi Vishkin University of Maryland College Park USA

ISBN: (纸本)9781450315722

We present novel work-optimal PRAM algorithms for Burrows-Wheeler (BW) compression and decompression of strings over a constant alphabet. For a string of length n, the depth of the compression algorithm is O(log2 n), and the depth of the corresponding decompression algorithm is O(log n). These appear to be the first polylogarithmic-time work-optimal parallel algorithms for any standard lossless compression *** algorithms for the individual stages of compression and decompression may also be of independent interest: 1. a novel O(log n)-time, O(n)-work PRAM algorithm for Huffman decoding; 2. original insights into the stages of the BW compression and decompression problems, bringing out parallelism that was not readily apparent. We then mapped such parallelism in interesting ways to elementary parallel routines that have O(log n)-time, O(n)-work solutions, such as: (i) prefix-sums problems with an appropriately-defined associative binary operator for several stages, and (ii) list ranking for the final stage of decompression (inverse blocksorting transform).Companion work reports empirical speedups of up to 25x for compression and up to 13x for decompression. This reflects a speedup of 70x over recent work on BW compression on GPUs.

关键词： burrows-wheeler lossless compression parallel pram

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