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检索条件"任意字段=Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures"

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Brief Announcement: Better Speedups for parallel Max-Flow 11

Brief Announcement: Better Speedups for Parallel Max-Flow

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23rd annual symposium on parallelism in algorithms and architectures

作者： Caragea, George C. Vishkin, Uzi Univ Maryland Dept Comp Sci College Pk MD 20742 USA

ISBN: (纸本)9781450307437

We present a parallel solution to the Maximum-Flow (Max-Flow) problem, suitable for a modern many-core architecture. We show that by starting from a PRAM algorithm, following an established "programmer's workflow" and targeting XMT, a PRAM-inspired many-core architecture, we achieve significantly higher speed-ups than previous approaches. Comparison with the fastest known serial max-flow implementation on a modern CPU demonstrates for the first time potential for orders-of-magnitude performance improvement for Max-Flow. Using XMT, the PRAM Max-Flow algorithm is also much easier to program than for other parallel platforms, contributing a powerful example toward dual validation of both PRAM algorithmics and XMT.

关键词： many-core processors max-flow parallel algorithms pram

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Brief Announcement: Communication Bounds for Heterogeneous architectures 11

Brief Announcement: Communication Bounds for Heterogeneous A...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Ballard, Grey Demmel, James Gearhart, Andrew UC Berkeley Berkeley CA USA

ISBN: (纸本)9781450307437

As the gap between the cost of communication (i.e., data movement) and computation continues to grow, the importance of pursuing algorithms which minimize communication also increases. Toward this end, we seek asymptotic communication lower bounds for general memory models and classes of algorithms. Recent work [2] has established lower bounds for a wide set of linear algebra algorithms on a sequential machine and on a parallel machine with identical processors. This work extends these previous bounds to a heterogeneous model in which processors access data and perform floating point operations at differing speeds. We also present an algorithm for dense matrix multiplication which attains the lower bound.

关键词： communication-avoiding heterogeneity

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Linear-Work Greedy parallel Approximate Set Cover and Variants 11

Linear-Work Greedy Parallel Approximate Set Cover and Varian...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Peng, Richard Tangwongsan, Kanat Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

We present parallel greedy approximation algorithms for set cover and related problems. These algorithms build on an algorithm for solving a graph problem we formulate and study called Maximal Nearly Independent Set (MANIS)-a graph abstraction of a key component in existing work on parallel set cover. We derive a randomized algorithm for MANIS that has O(m) work and O(log(2)m) depth on input with m edges. Using MANIS, we obtain RNC algorithms that yield a (1 + epsilon)H-n-approximation for set cover, a (1 - 1/e - epsilon)-approximation for max cover and a (4 + epsilon)-approximation for min-sum set cover all in linear work;and an O(log*n)-approximation for asymmetric k-center for k <= log(O(1)) n and a (1.861 + epsilon)-approximation for metric facility location both in essentially the same work bounds as their sequential counterparts.

关键词： parallel algorithms approximations algorithms set cover max cover facility location

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SPAA'11 - proceedings of the 23rd annual symposium on parallelism in algorithms and architectures

SPAA'11 - Proceedings of the 23rd Annual Symposium on Parall...

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23rd acm symposium on parallelism in algorithms and architectures, SPAA'11

ISBN: (纸本)9781450307437

The proceedings contain 50 papers. The topics discussed include: graph expansion and communication costs of fast matrix multiplication;near linear-work parallel SDD solvers, low-diameter decomposition, and low-stretch subgraphs;linear-work greedy parallel approximate set cover and variants;optimizing hybrid transactional memory: the importance of nonspeculative operations;parallelism and data movement characterization of contemporary application classes;work-stealing for mixed-mode parallelism by deterministic team-building;full reversal routing as a linear dynamical system;reclaiming the energy of a schedule, models and algorithms;a tight runtime bound for synchronous gathering of autonomous robots with limited visibility;convergence of local communication chain strategies via linear transformations: or how to trade locality for speed;and convergence to equilibrium of logit dynamics for strategic games.

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parallelism in Dynamic Well-Spaced Point Sets 11

Parallelism in Dynamic Well-Spaced Point Sets

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23rd annual symposium on parallelism in algorithms and architectures

作者： Acar, Umut A. Cotter, Andrew Hudson, Benoit Tuerkoglu, Duru Max Planck Inst Software Syst Kaiserslautern Germany

ISBN: (纸本)9781450307437

parallel algorithms and dynamic algorithms possess an interesting duality property: compared to sequential algorithms, parallel algorithms improve run-time while preserving work, while dynamic algorithms improve work but typically offer no parallelism.. Although they are often considered separately, parallel and dynamic algorithms employ similar design techniques. They both identify parts of the computation that are independent of each other. This suggests that dynamic algorithms could be parallelized to improve work efficiency while preserving fast parallel run-time. In this paper, we parallelize a dynamic algorithm for well-spaced point sets, an important problem related to mesh refinement in computational geometry. Our parallel dynamic algorithm computes a well-spaced superset of a dynamically changing set of points, allowing arbitrary dynamic modifications to the input set. On an EREW PRAM, our algorithm processes batches of k modifications such as insertions and deletions in O(k log Delta) total work and in O(log Delta) parallel time using k processors, where Delta is the geometric spread of the data, while ensuring that the output is always within a constant factor of the optimal size. EREW PRAM model is quite different from actual hardware such as modern multiprocessors. We therefore describe techniques for implementing our algorithm on modern multi-core computers and provide a prototype implementation. Our empirical evaluation shows that our algorithm can be practical, yielding a large degree of parallelism and good speedups.

关键词： parallel batch dynamic updates multithreading voronoi diagrams well-spaced point sets self-adjusting computation mesh refinement

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The Pochoir Stencil Compiler 11

The Pochoir Stencil Compiler

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23rd annual symposium on parallelism in algorithms and architectures

作者： Tang, Yuan Chowdhury, Rezaul Kuszmaul, Bradley C. Luk, Chi-Keung Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781450307437

A stencil computation repeatedly updates each point of a d-dimensional grid as a function of itself and its near neighbors. parallel cache-efficient stencil algorithms based on "trapezoidal decompositions" are known, but most programmers find them difficult to write. The Pochoir stencil compiler allows a programmer to write a simple specification of a stencil in a domain-specific stencil language embedded in C++ which the Pochoir compiler then translates into high-performing Cilk code that employs an efficient parallel cache-oblivious algorithm. Pochoir supports general d-dimensional stencils and handles both periodic and aperiodic boundary conditions in one unified algorithm. The Pochoir system provides a C++ template library that allows the user's stencil specification to be executed directly in C++ without the Pochoir compiler (albeit more slowly), which simplifies user debugging and greatly simplified the implementation of the Pochoir compiler itself. A host of stencil benchmarks run on a modern multicore machine demonstrates that Pochoir outperforms standard parallel-loop implementations, typically running 2-10 times faster. The algorithm behind Pochoir improves on prior cache-efficient algorithms on multidimensional grids by making "hyperspace" cuts, which yield asymptotically more parallelism for the same cache efficiency.

关键词： C plus cache-oblivious algorithm Cilk compiler embedded domain-specific language multicore parallel computation stencil trapezoidal decomposition

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Near Linear-Work parallel SDD Solvers, Low-Diameter Decomposition, and Low-Stretch Subgraphs 11

Near Linear-Work Parallel SDD Solvers, Low-Diameter Decompos...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Gupta, Anupam Koutis, Ioannis Miller, Gary L. Peng, Richard Tangwongsan, Kanat Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

This paper presents the design and analysis of a near linear-work parallel algorithm for solving symmetric diagonally dominant (SDD) linear systems. On input of a SDD n-by-n matrix A with m non-zero entries and a vector h, our algorithm computes a vector (x) over tilde;such that parallel to(x) over tilde - A(+)b parallel to A <= epsilon . parallel to A(+)b parallel to A in O(m log(O(1)) n log 1/epsilon) work and O(m(1/3+theta) log 1/epsilon) depth for any fixed theta > 0. The algorithm relies on a parallel algorithm for generating low-stretch spanning trees or spanning subgraphs. To this end, we first develop a parallel decomposition algorithm that in polylogarithmic depth and (O) over tilde vertical bar E vertical bar) work(1), partitions a graph into components with polylogarithmic diameter such that only a small fraction of the original edges are between the components. This can be used to generate low-stretch spanning trees with average stretch O(n(alpha)) in O(n(1+alpha)) work and O(n(alpha)) depth. Alternatively, it can be used to generate spanning subgraphs with polylogarithmic average stretch in O(vertical bar E vertical bar) work and polylogarithmic depth. We apply this subgraph construction to derive our solver. By using the linear system solver in known applications, our results imply improved parallel randomized algorithms for several problems, including single-source shortest paths, maximum flow, min-cost flow, and approximate max-flow.

关键词： parallel algorithms linear systems low-stretch spanning trees low-stretch subgraphs low-diameter decomposition

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Brief announcement: RedRem: A parallel redundancy remover 11

Brief announcement: RedRem: A parallel redundancy remover

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proceedings of the twenty-third annual acm symposium on parallelism in algorithms and architectures

作者： Acharya, Hrishikesh Gouda, Mohamed University of Texas at Austin Austin TX United States National Science Foundation Washington DC United States

ISBN: (纸本)9781450307437

Policies defined by a sequence of predicate-decision rules, with first-match semantics, are widely used;a notable example is their use in firewalls, where the rules are used to decide whether to accept or discard each packet. Owing to the critical importance of correctness of such policies, as well as the need for high performance, they have been the subject of considerable analysis. In earlier work, we have demonstrated that the problem of removing redundant rules from firewalls is theoretically equivalent to verifying that a firewall satisfies a property, and proposed that this theorem be used to build a high performance redundancy remover. In this paper, we realize this promise, and build a fast linear-space redundancy remover, one to three orders of magnitude faster than current approaches. Further, we show that our algorithm is easy to parallelize- there exists a natural way to partition a large instance of the problem into independent small ones. © 2011 Authors.

关键词： Redundancy

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Scheduling Irregular parallel Computations on Hierarchical Caches 11

Scheduling Irregular Parallel Computations on Hierarchical C...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Fineman, Jeremy T. Gibbons, Phillip B. Simhadri, Harsha Vardhan Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

For nested-parallel computations with low depth (span, critical path length) analyzing the work, depth, and sequential cache complexity suffices to attain reasonably strong bounds on the parallel runtime and cache complexity on machine models with either shared or private caches. These bounds, however, do not extend to general hierarchical caches, due to limitations in (i) the cache-oblivious (CO) model used to analyze cache complexity and (ii) the schedulers used to map computation tasks to processors. This paper presents the parallel cache-oblivious (PCO) model, a relatively simple modification to the CO model that can be used to account for costs on a broad range of cache hierarchies. The first change is to avoid capturing artificial data sharing among parallel threads, and the second is to account for parallelism-memory imbalances within tasks. Despite the more restrictive nature of PCO compared to CO, many algorithms have the same asymptotic cache complexity bounds. The paper then describes a new scheduler for hierarchical caches, which extends recent work on "space-bounded schedulers" to allow for computations with arbitrary work imbalance among parallel subtasks. This scheduler attains provably good cache performance and runtime on parallel machine models with hierarchical caches, for nested-parallel computations analyzed using the PCO model. We show that under reasonable assumptions our scheduler is "work efficient" in the sense that the cost of the cache misses are evenly balanced across the processors-i.e., the runtime can be determined within a constant factor by taking the total cost of the cache misses analyzed for a computation and dividing it by the number of processors. In contrast, to further support our model, we show that no scheduler can achieve such bounds (optimizing for both cache misses and runtime) if work, depth, and sequential cache complexity are the only parameters used to analyze a computation.

关键词： parallel hierarchical memory Cost models Schedulers Analysis of parallel algorithms Cache complexity

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Scalable Power Control for Many-Core architectures Running Multi-threaded Applications 11

Scalable Power Control for Many-Core Architectures Running M...

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38th annual International symposium on Computer Architecture

作者： Ma, Kai Li, Xue Chen, Ming Wang, Xiaorui Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA

ISBN: (纸本)9781450304726

Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cannot scale well with the rapidly increasing level of core integration. While a few recent studies propose power control algorithms for many-core architectures, those solutions assume that the workload of every core is independent and therefore cannot effectively allocate power based on thread criticality to accelerate multi-threaded parallel applications, which are expected to be the primary workloads of many-core architectures. This paper presents a scalable power control solution for many-core microprocessors that is specifically designed to handle realistic workloads, i.e., a mixed group of single-threaded and multi-threaded applications. Our solution features a three-layer design. First, we adopt control theory to precisely control the power of the entire chip to its chip-level budget by adjusting the aggregated frequency of all the cores on the chip. Second, we dynamically group cores running the same applications and then partition the chip-level aggregated frequency quota among different groups for optimized overall microprocessor performance. Finally, we partition the group-level frequency quota among the cores in each group based on the measured thread criticality for shorter application completion time. As a result, our solution can optimize the microprocessor performance while precisely limiting the chip-level power consumption below the desired budget. Empirical results on a 12-core hardware testbed show that our control solution can provide precise power control, as well as 17% and 11% better application performance than two state-of-the-art solutions, on average, for mixed PARSEC and SPEC benchmarks. Furthermore, our extensive simulation results for 32, 64, and 128 cores, as well as overhead analysis for up to 4,096 cores, demonstrate that our solution is highly scalable to many

关键词： Chip multiprocessor many-core architecture power control power capping thread criticality scalability control theory

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