We analyze the scheduling aspects of database queries submitted to an abstract model of a very large distributed system. The essential elements of this model are: (a) a finite number of identical processing nodes with...
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We analyze the scheduling aspects of database queries submitted to an abstract model of a very large distributed system. The essential elements of this model are: (a) a finite number of identical processing nodes with limited storage capacity, (b) a finite number of queries to be serviced, (c) a very large read-only data set that is shared by all queries and (d) a fixed inter-node communication latency. This framework models an important class of applications that use distributed processing of very large data sets. Examples of these applications exist in the very large database and multimedia problem domains. To meet the objective of minimizing flow time of queries while exploiting inter-query locality, various heuristics are proposed and evaluated through extensive simulation.
Most experimental studies of the performance of parallelsimulation protocols use speedup or number of events processed per unit time as the performance metric. Although helpful in evaluating the usefulness of paralle...
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ISBN:
(纸本)9780818675393
Most experimental studies of the performance of parallelsimulation protocols use speedup or number of events processed per unit time as the performance metric. Although helpful in evaluating the usefulness of parallelsimulation for a given simulation model, these metrics tell us little about the efficiency of the simulation protocol used. In this paper, we describe an Ideal simulation Protocol (ISP), based on the concept of critical path, which experimentally computes the best possible execution time for a simulation model on a given parallel architecture. Since ISP computes the bound by actually executing the model on the given parallel architecture, it is much more realistic than that computed by a uniprocessor critical path analysis. The paper illustrates, using parameterized synthetic benchmarks, how an ISP-based performance evaluation can lead to much better insights into the performance of parallelsimulation protocols than what would be gained from speedup graphs alone.
This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems prototyping applied to an industrial application. The environment provides following features: distributed Hw/Sw c...
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This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems prototyping applied to an industrial application. The environment provides following features: distributed Hw/Sw cosimulation, automatic Hw/Sw interface generation, Hw elements can be described at different levels of abstraction and generic/specific Sw debuggers can be used. Starting from a brief description of the interface of the interconnected modules the tool automatically produces the link between Hw and Sw parts. In addition, the environment is very easy to use, even for complex systems that may include several Sw (C) modules and several Hw (VHDL) modules running in parallel. Applied to a large industrial multi-processor system, this method appeared reliable and efficient, providing important benefits in hardware-software codesign: better design environment and reduced time to validate.
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the difficulty in parallel programming persists and there is increasing demand for high level...
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ISBN:
(纸本)9780818675393
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the difficulty in parallel programming persists and there is increasing demand for high level support for building discrete event models to execute on such platforms. We present a parallel DEVS-based (Discrete Event System Specification) simulation environment that can execute on distributed memory multicomputer systems with benchmarking results of a class of high resolution, large scale ecosystem models. Underlying the environment is a parallel container class library for hiding the details of message passing technology while providing high level abstractions for hierarchical, modular DEVS models. The C++ implementation working on the Thinking Machines CM-5 demonstrates that the desire for high level modeling support need not be irreconcilable with sustained high performance.
Heterogeneous network computing allows the development of a single complex application using a distributed network of machines; these machines may differ in terms of CPU and memory capacity and/or architecture and spe...
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Heterogeneous network computing allows the development of a single complex application using a distributed network of machines; these machines may differ in terms of CPU and memory capacity and/or architecture and specialized functions. We present a modeling technique, based on generalized stochastic Petri nets (GSPNs), for the performance analysis of applications targeted to this class of systems (heterogeneous applications). We illustrate the use of the proposed technique by modeling and analyzing the CASA 3D-REACT heterogeneous application.
A new Conservative algorithm for both parallel and sequential simulation of networks is described. The technique is motivated by the construction of a high performance simulator for ATM networks. It permits very fast ...
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ISBN:
(纸本)9780818675393
A new Conservative algorithm for both parallel and sequential simulation of networks is described. The technique is motivated by the construction of a high performance simulator for ATM networks. It permits very fast execution of models of ATM systems, both sequentially and in parallel. A simple analysis of the performance of the system is made. Initial performance results from parallel and sequential implementations are presented and compared with comparable results from an optimistic TimeWarp based simulator. It is shown that the conservative simulator performs well when the "density" of messages in the simulated system is high, a condition which is likely to hold in many interesting ATM scenarios.
The Annai integrated tool environment helps exploit the inherent power of distributed-memory parallel computers with standardized languages and convenient programming support. Portable application development is suppo...
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The Annai integrated tool environment helps exploit the inherent power of distributed-memory parallel computers with standardized languages and convenient programming support. Portable application development is supported in High Performance Fortran and/or with explicit message-passing, using MPI as the machine interface. Integration within a unified tool environment allows the performance monitor and analyzer (PMA) component to interact with source code browsers and the loaded executable on the same terms as when using the parallel debugger. Data distribution and other program information furnished by the parallelization support and compilation systems is also exploited for additional insight. Powerful, directed analysis and interactive graphical summaries address scalability, while detailed charts of the time-varying behavior of individual processes and communication events can also be browsed when desired, always retaining essential reference to the original program source code.
Many systems rely on the ability to rollback (or restore) parts of the system state to undo or recover from undesired or erroneous computations. Examples of such systems include fault tolerant systems with checkpointi...
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ISBN:
(纸本)9780818675393
Many systems rely on the ability to rollback (or restore) parts of the system state to undo or recover from undesired or erroneous computations. Examples of such systems include fault tolerant systems with checkpointing, editors with undo capabilities, transaction and data base systems and optimistically synchronized parallel and distributedsimulations. An essential part of such systems is the state saving mechanism. It should not only allow efficient state saving, but also support efficient state restoration in case of roll back. Furthermore, it is often a requirement that this mechanism is transparent to the user. In this paper we present a method to implement a transparent incremental state saving mechanism in an optimistically synchronized parallel discrete event simulation system based on the Time Warp mechanism. The usefulness of this approach is demonstrated by simulations of large, detailed, realistic FCA and a DCA-like cellular phone systems.
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by ...
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ISBN:
(纸本)9780818675393
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.
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