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检索条件"任意字段=Proceedings of the seventh workshop on Parallel and distributed simulation"

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Efficient massively parallel simulation of dynamic channel assignment schemes for wireless cellular communications

Efficient massively parallel simulation of dynamic channel a...

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International Symposium on Modeling, Analysis and simulation of Computer and Telecommunication Systems (MASCOTS)

作者： A.G. Greenberg B.D. Lubachevsky P.E. Wright D.M. Nicol AT and T Bell Laboratories Inc. USA College of William and Mary USA

Fast, efficient parallel algorithms are presented for discrete event simulations of dynamic channel assignment schemes for wireless cellular communication networks. The driving events are call arrivals and departures, in continuous time, to cells geographically distributed across the service area. A dynamic channel assignment scheme decides which call arrivals to accept, and which channels to allocate to the accepted calls, attempting to minimize call blocking while ensuring co-channel interference is tolerably low. Specifically, the scheme ensures that the same channel is used concurrently at different cells only if the pairwise distances between those cells are sufficiently large. Much of the complexity of the system comes from ensuring this separation. The network is modeled as a system of interacting continuous time automata, each corresponding to a cell. To simulate the model, we use conservative methods; i.e., methods in which no errors occur in the course of the simulation and so no rollback or relaxation is needed. Implemented on a 16 K processor MasPar MP-1, an elegant and simple technique provides speedups of about 15/spl times/ over an optimized serial simulation running on a high speed workstation. A drawback of this technique, typical of conservative methods, is that processor utilization is rather low. To overcome this, we developed new methods that exploit slackness in event dependencies over short intervals of time, thereby raising the utilization to above 50% and the speedup over the optimized serial code to about 120/spl times/ with respect to the workstation simulation.< >

关键词： Discrete event simulation Resource management Cellular networks Workstations Wireless communication Automata Land mobile radio cellular systems Educational institutions parallel algorithms Communication networks

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Empirical study of parallel trace-driven LRU cache simulators 95

Empirical study of parallel trace-driven LRU cache simulator...

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proceedings of the ninth workshop on parallel and distributed simulation

作者： David Nicol Eric Carr Department of Computer Science College of William and Mary Williamsburg VA Department of Math and Computer Science Carleton College Northfield MN

ISBN: (纸本)9780818671203

This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs.

关键词： associative cache content-addressable storage storage management cache storage parallel algorithms SPEC92 benchmark programs parallel trace-driven LRU cache simulators Least-Recently-Used replacement policy Intel Paragon efficient serial algorithm MasPar MP-2 virtual machines

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Performance comparison of real-time architectures using simulation

Performance comparison of real-time architectures using simu...

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IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Heejo Lee K. Toda Jong Kim K. Nishida E. Takahashi Y. Yamaguchi Department of Computer Science & Engineering Pohang University of Science and Technology Pohang South Korea Electro Technical Laboratory Tsukuba Japan

This paper presents a performance comparison of real-time system architectures. A discrete event-driven, task-based simulator is developed for evaluating the performance of parallel and distributed real-time systems. Real-time system components such as processor, network architectures, and scheduling policy are included in the simulator. simulation results show that priority-based communication and scheduling are more suitable for real-time systems than FIFO-based. The strategy of having a dedicated processor, which produces no effect on task execution by scheduling and packet/interrupt handling, is proven to enhance schedulability and predictability. This paper suggests a method for finding an appropriate real-time architecture for users having real-time requirements through the performance prediction of real-time systems.

关键词： Real time systems Discrete event simulation Job shop scheduling Processor scheduling Computational modeling Predictive models Computer architecture Computer aided manufacturing Computer simulation Computer science

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Effectiveness of global event queues in rollback reduction and load balancing 95

Effectiveness of global event queues in rollback reduction a...

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Sushil K. Prasad Basem Naqib Mathematics and Computer Science Georgia State University Atlanta

ISBN: (纸本)9780818671203

Compared to highly optimized optimistic simulators which use local event queues for individual processors on a shared-memory computer, we demonstrate that employing a single global event queue drastically reduces the number of rollbacks, brings down the storage requirements, and achieves superior load balance. On a bus-based Silicon Graphics multiprocessor, these virtues consistently translated into faster execution times and higher speedups on those synthetic networks of medium- to coarse-grained logical processes which were ridden with rollbacks and load imbalance on local-queue-based simulators. A dynamic randomization-based load distribution scheme for local-event-queue simulators is also shown to be an effective improvement.

关键词： discrete event simulation global event queues shared-memory computer global event queue rollback reduction load balancing parallel algorithms data structures shared memory systems resource allocation load distribution scheme

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The ultimate bead counter: efficient massively parallel simulation of ballistic deposition 95

The ultimate bead counter: efficient massively parallel simu...

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Boris D. Lubachevsky Vladimir Privman Subhas C. Roy AT&T Bell Laboratories 600 Mountain Avenue Murray Hill NJ Department of Physics Clarkson Univercity Potsdam NY Department of Computer Science College of William and Mary Williamsburg VA

ISBN: (纸本)9780818671203

We simulate ballistic particle deposition wherein a large number of spherical particles are “dropped” vertically over a planar horizontal surface. Upon first contact (with the surface or with a previously deposited particle) each particle stops. This model helps material scientists to study the adsorption and sediment formation [1]. The model is sequential, with particles deposited one by one. We have found an equivalent formulation using a continuous time random process and we simulate the latter in parallel using a method similar to the one previously employed for simulating Ising spins [2]. We augment the parallel algorithm for simulating Ising spins with several techniques aimed at the increase of efficiency of producing the particle configuration and statistics collection. Some of these techniques are similar to [3], [4], [5]. We implement the resulting algorithm on a 16K PE MasPar MP-1 and a 4K PE MasPar MP-2. The parallel code runs on MasPar computers two orders of magnitude faster than an optimized sequential code runs on a fast workstation.

关键词： massively parallel simulation 16K PE MasPar MP-1 parallel algorithm Ising model digital simulation atom-surface impact parallel algorithms statistics collection physics computing particle configuration equivalent formulation ultimate bead counter material scientists Ising spins simulation 4K PE MasPar MP-2 continuous time random process ballistic deposition sediment formation adsorption sputter deposition

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The treatment of state in optimistic systems 95

The treatment of state in optimistic systems

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proceedings of the ninth workshop on parallel and distributed simulation

作者： David Bruce Defence Research Agency st. Andrews Road Malvern Worcestershire WR14 3PS United Kingdom

ISBN: (纸本)9780818671203

Optimistic computation methods typically save copies of objects' state information, so that they can recover from erroneous “over-optimistic” computations. Such state saving is generally time and space consuming, and can be rather complicated both to implement and to use.I show how the data structure community's theory of persistence can be used not only to analyse and explain the treatment of state in optimistic systems, but also as a simple yet general mechanism for performing the necessary state saving with minimal impact on application *** results based on a benchmark application and an existing optimistic simulator are presented, showing that providing support for fully general object states is a realistic and practical option. In addition, I show how some existing state saving techniques—including support for shared state—can be derived, and discuss a number of ways in which the model might be extended.

关键词： state saving optimistic methods parallel discrete event simulation persistent data structures

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SGTNE: semi-global time of the next event algorithm 95

SGTNE: semi-global time of the next event algorithm

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Azzedine Boukerche Carl Tropper School of Computer Science McGill University Montreal Canada H3A-2A7

ISBN: (纸本)9780818671203

This paper describes an extension of the TNE algorithm, the objective of which is to increase its parallelism and to break the inter-processor deadlocks inherent with the use of TNE. The algorithm, which we call the SGTNE algorithm (Semi Global TNE), is executed over a cluster of processors as opposed to TNE, which is executed over a cluster of processes assigned to a single processor. SGTNE helps to break the inter-processor deadlocks by executing a shortest path algorithm over a snapshot of the LPs in a cluster of processors. This paper discusses the algorithm and its implementation and reports on the performance results of simulations of a partitioned FCFS queueing network model executed on the Intel Paragon A4 multiprocessor machine. We also examine the impact of partitioning on the efficient implementation of the SGTNE algorithm. The results obtained indicate that SGTNE yields good speedups and that a partitioning which makes use of a strongly connected component algorithm results in a reduction of 30% in the running time of a simulation when compared to simple partitioning strategies. The results also indicate that SGTNE outperforms TNE.

关键词： discrete event simulation SGTNE partitioning parallel algorithms FCFS queueing network model inter-processor deadlock parallelism shortest path algorithm performance results

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Buffer management in shared-memory Time Warp systems 95

Buffer management in shared-memory Time Warp systems

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Richard M. Fujimoto Kiran S. Panesar College of Computing Georgia Institute of Technology Atlanta GA

ISBN: (纸本)9780818671203

Mechanisms for managing message buffers in Time Warp parallel simulations executing on cache-coherent shared-memory multiprocessors are studied. Two simple buffer management strategies called the sender pool and receiver pool mechanisms are examined with respect to their efficiency, and in particular, their interaction with multiprocessor cache-coherence protocols. Measurements of implementations on a Kendall Square Research KSR-2 machine using both synthetic workloads and benchmark applications demonstrate that sender pools offer significant performance advantages over receiver pools. However, it is also observed that both schemes, especially the sender pool mechanism, are prone to severe performance degradations due to poor locality of reference in large simulations using substantial amounts of message buffer memory. A third strategy called the partitioned buffer pool approach is proposed that exploits the advantages of sender pools, but exhibits much better locality. Measurements of this approach indicate that the partitioned pool mechanism yields substantially better performance than both the sender and receiver pool schemes for large-scale, small-granularity parallel simulation *** central conclusions from this study are: (1) buffer management strategies play an important role in determining the overall efficiency of multiprocessor-based parallel simulators, and (2) the partitioned buffer pool organization offers significantly better performance than the sender and receiver pool schemes. These studies demonstrate that poor performance may result if proper attention is not paid to realizing an efficient buffer management mechanism.

关键词： message buffers multiprocessor-based parallel simulators buffer management message buffer memory multiprocessor cache-coherence protocols Kendall Square Research KSR-2 machine mall-granularity parallel simulation applications discrete event simulation cache-coherent shared-memory multiprocessors multiprocessing programs shared memory systems buffer storage message passing severe performance degradations sender pool time warp simulation receiver pool storage management partitioned pool mechanism shared-memory time warp systems partitioned buffer pool approach

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Comparative analysis of periodic state saving techniques in time warp simulators 95

Comparative analysis of periodic state saving techniques in ...

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Josef Fleischmann Philip A. Wilsey Institute of Electronic Design Automation Technical University of Munich D-80290 Munich Germany Center for Digital Systems Engineering Dept of ECECS PO Box 210030 Cincinnati Ohio

ISBN: (纸本)9780818671203

Checkpointing in a time warp synchronized parallel simulator is a necessary and potentially expensive operation. In the simple case, a time warp simulator checkpoints every χ events, for some fixed value χ. For larger values of χ, the simulator requires less overhead for saving the state, but incurs an increased latency during rollback. Thus, the problem is to balance the time to save states against the time to coast forward upon rollback. Unfortunately, a static determination of a optimal value for χ is very difficult and can vary widely, even between closely related instances of a time warp simulator. Furthermore, the optimal checkpoint interval may actually vary over the lifetime of the *** address these problems, several investigators have proposed dynamically adjusting the checkpoint interval χ as the simulation progresses. This paper analyzes three previous techniques for dynamically sizing checkpoint intervals and presents a new, heuristic algorithm for this purpose. All four techniques are implemented in a common application domain (digital system simulation from VHDL descriptions) and a direct comparison between the algorithms is performed. The results show a significant difference in the performance of the implemented algorithms. However, in virtually all cases, the dynamic algorithms performed near or better than the best static value. Furthermore, the best algorithms performed as much as 12% better than the best static value.

关键词： latency discrete event simulation time warp simulation periodic state saving techniques hardware description languages heuristic algorithm VHDL descriptions checkpointing rollback time warp simulators

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Clustered time warp and logic simulation 95

Clustered time warp and logic simulation

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proceedings of the ninth workshop on parallel and distributed simulation

作者： Hervé Avril Carl Tropper School of Computer Science McGill University Montréal Canada H3A 2A7 and Hutchison Avenue Software Corporation Montréal Canada School of Computer Science McGill University Montréal Canada H3A 2A7

ISBN: (纸本)9780818671203

We present, in this paper, a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the cluster. Time Warp is, of course, traditionally implemented between individual LPs. The algorithm was implemented in a digital logic simulator, and its performance compared to that of Time *** upon this platform we develop a family of three checkpointing algorithms, each of which occupies a different point in the spectrum of possible trade-offs between memory usage and execution time. The algorithms were implemented on several digital logic circuits and their speed, number of states saved and maximal memory consumption were compared to those of Time Warp. One of the algorithms saved between 35 and 50% of the maximal memory consumed by Time Warp (depending upon the number of processors used), while the other two decreased the maximal usage up to 30%. The latter two algorithms exhibited a speed comparable to Time Warp, while the first algorithm was 30-60% *** algorithms are also simpler to implement than optimal checkpointing algorithms.

关键词： circuit analysis computing digital logic circuits hybrid algorithm sequential algorithm clustered time warp logic CAD time warp simulation checkpointing algorithms digital logic simulator logic simulation maximal memory consumption

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