parallel discrete event simulation algorithms are usually based on time stamp ordering of events. distributed virtual environment (DVE) applications such as DIS typically use unordered event delivery. A partial order ...
ISBN:
(纸本)9780769501550
parallel discrete event simulation algorithms are usually based on time stamp ordering of events. distributed virtual environment (DVE) applications such as DIS typically use unordered event delivery. A partial order called approximate time (AT) is proposed to order events in both domains, facilitating reuse of simulations across DVE and analysis applications. A variation on AT-order called approximate time causal (ATC) order is also described. Synchronization algorithms to realize these orderings are presented as well as performance measurements on a workstation cluster. A long-term goal of this work is to use AT and ATC order to exploit temporal uncertainty in the model to achieve efficient conservative parallelsimulation despite little or no lookahead, a longstanding problem in the field.
We present a software approach, namely fast-software-checkpointing (FSC), to reduce the running time of the state saving protocol in optimistic parallel discrete event simulation. The idea behind FSC is to use the ins...
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We present a software approach, namely fast-software-checkpointing (FSC), to reduce the running time of the state saving protocol in optimistic parallel discrete event simulation. The idea behind FSC is to use the instructions performed during the execution of an event as part of the state saving protocol, hence the total number of instructions due to state saving is reduced. Under FSC the time for saving the state of a logical process prior to the execution of an event E requires an amount of time proportional to the amount of state variables not updated by E's execution, as only these variables must be copied. This outlines that FSC shows some dualism with respect to incremental state saving. We show, however that there exists a basic difference between the two solutions as in FSC some of the state saving instructions are actually event routine instructions, while in incremental state saving they are only added and mixed to the latter ones. We also present a simple software architecture to support FSC and simulation results to demonstrate the effectiveness of such solution. The obtained data show that FSC, combined with a sparse state saving strategy may represent the best checkpointing solution in case of both medium/small state granularity simulations and large state granularity simulations even with small (but non-minimal) portions of the state updated by event execution. FSC may result therefore suited for a wide class of simulation problems.
Discrete event simulation is widely used within the networking community for purposes such as demonstrating the validity of network protocols and architectures. Depending on the level of detail modeled within the simu...
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Discrete event simulation is widely used within the networking community for purposes such as demonstrating the validity of network protocols and architectures. Depending on the level of detail modeled within the simulation, the running time and memory requirements can be excessive. The goal of our research is to develop and demonstrate a practical, scalable approach to parallel and distributedsimulation that will enable widespread reuse of sequential network simulation models and software. We focus on an approach to parallelization where an existing network simulator is used to build models of subnetworks that are composed to create simulations of larger networks. Changes to the original simulator care minimized, enabling the parallel simulator to easily track enhancements to the sequential version. We describe our lessons learned in applying this approach to the publicly available ns software package (McCanne and Floyd, 1997) and converting it to run in a parallel fashion on a network of workstations. This activity highlights a number of important problems, from the standpoint of how to parallelize an existing serial simulation model and achieving acceptable parallel performance.
This paper presents the SEEDS simulation environment for the evaluation of distributed traffic control systems. Starting with an overview of the general simulator architecture, the software modules and the derived har...
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This paper presents the SEEDS simulation environment for the evaluation of distributed traffic control systems. Starting with an overview of the general simulator architecture, the software modules and the derived hardware architecture of the simulation environment are described with respect to performance requirements. The communication architecture of the SEEDS simulator is based on the CORBA standard and the DIS simulation protocol. With the SEEDS prototype simulating airport ground-traffic, performance measurements evaluating critical design and implementation decisions are described. The main aspects of the performance analysis are the attained application performance using CORBA and DIS as communication middleware, and the scalability of the overall approach. The evaluation shows the appropriateness of the design of the simulation environment and the derived hard- and software architecture, which is flexible and open to further extensions. Moreover the combination of CORBA and DIS provides a suited platform for distributed interactive simulation purposes because of the adequate performance, high scalability, and the high-level programming model which allows to rapidly develop and maintain complex distributed applications with high-performance requirements.
Interval temporal logic (ITL) is a real-time logic for specifying and verifying real-time systems. In this paper, ITL is used to specify a concurrent real-time system: an assembly line which is an abstract model of in...
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Interval temporal logic (ITL) is a real-time logic for specifying and verifying real-time systems. In this paper, ITL is used to specify a concurrent real-time system: an assembly line which is an abstract model of industrial robot control systems. We can specify the abstract properties of the system in ITL as well as the system design using the executable subset of ITL, Tempura. Compared with other approaches, the first advantage of this methodology is that the concurrent real-time systems can be naturally specified in a true concurrent model rather than an interleaving model. The second is that the specification of the system design is executable so that the simulation can be obtained in the same formal framework. Therefore, both the properties of the system and the consistency of the specification can be checked before verification.
The Extended Air Defense Testbed (EADTB), is a comprehensive, high- and mixed-level-of-detail, environment for modeling weapon system entities and interactions. Due to the complexity of the models and large scenario s...
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The Extended Air Defense Testbed (EADTB), is a comprehensive, high- and mixed-level-of-detail, environment for modeling weapon system entities and interactions. Due to the complexity of the models and large scenario sizes, in its current single-threaded form, EADTB is limited in run-time speed. Our goal is to speed up the simulation without re-architecture or re-implementation of the models which comprise 1.76 million lines of Ada code, and without altering model behavior or compromising repeatability and causality. Our work demonstrates that the use of optimistic scheduling techniques and its derivatives, offers the best alternative for object-based systems like EADTB. Specifically we have retrofitted and integrated the same representative pseudo-EADTB prototype with two different object-oriented optimistic scheduling engines (SPEEDES and TEMPO/Thema). We discuss the required architectural and behavioral features of a simulation to allow this retrofit, the issues of C++ to Ada language interfaces, and the employment of the basic services of the optimistic scheduling engines in this environment. Experimental results suggest that order-of-magnitude speed-up is feasible through parallelization, and is scalable to larger experiments simply by adding hardware.
High performance clusters (HPCs) based on commodity hardware are becoming more and more popular in the parallel computing community. These new platforms offer hardware capable of a very low latency and a very high thr...
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High performance clusters (HPCs) based on commodity hardware are becoming more and more popular in the parallel computing community. These new platforms offer hardware capable of a very low latency and a very high throughput at an unbeatable cost, making them attractive for a large variety of parallel and distributed applications. With adequate communication software, HPCs have the potential to achieve a level of performance similar to massively parallel computers. However for parallel applications that present a high communication/computation ratio, it is still essential to provide the lowest latency in order to minimize the communication overhead. We are investigating message aggregation techniques to improve parallelsimulations of fine-grain ATM communication network models. Even if message aggregation is a well-known solution for improving the communication performance of high latency interconnection networks, the complex interaction between message aggregation and the underlying communication software is often ignored. We show that message aggregation must carefully take into account the characteristics of the communication software to be efficient on an HPC. This methodology can be applied as a preliminary step to tune a message aggregation algorithm for a given combination of hardware architecture and communication software layer.
There are at least three major obstacles thwarting wide-spread adoption of parallel discrete-event simulation (a) lack of need, (b) lack of tools, (c) lack of predictability in behavior and performance. The plain trut...
ISBN:
(纸本)9780769501550
There are at least three major obstacles thwarting wide-spread adoption of parallel discrete-event simulation (a) lack of need, (b) lack of tools, (c) lack of predictability in behavior and performance. The plain truth is that most simulation studies can be adequately done on ordinary serial computers. parallelsimulation tools are products of re-search efforts, and simply don't stand up to the demands of modern software engineering. The results of 20 years of research in parallelsimulation reveal it to be a highly complex endevour, with performance results very much dependent on implementation details and model characteristics.
Most successful examples of parallelsimulation models were developed for parallel execution, from the beginning. A number of simulation models are designed only for sequential simulation, even in languages like PARSE...
ISBN:
(纸本)9780769501550
Most successful examples of parallelsimulation models were developed for parallel execution, from the beginning. A number of simulation models are designed only for sequential simulation, even in languages like PARSEC, that support both sequential and parallelsimulation algorithms. Converting such simulation models to a form that yields good performance with a parallel implementation can be non-trivial. In this paper we describe a case study showing this conversion process for a simulation model of replicated file systems. The details of the major steps taken in converting the simulation into a parallelsimulation are presented: correctness changes; performance changes such as communication topology simplification and lookahead specification; and modeling changes to eliminate performance bottlenecks. The details and performance improvements of each step are presented in this paper.
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