Performance of VHDL simulation is a critical issue in electronic circuit design and is hard to achieve due to the complexity of the language and the different abstraction levels. This paper presents a system for perfo...
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ISBN:
(纸本)1565550277
Performance of VHDL simulation is a critical issue in electronic circuit design and is hard to achieve due to the complexity of the language and the different abstraction levels. This paper presents a system for performance evaluation of distributed-time VHDL simulation based on the analysis of simulation traces. The system allows to model different architectures, interconnection topologies and simulation algorithms. The main tools are a VHDL analyzer to extract dependencies, and a trace-driven simulator to evaluate the execution time on a given architecture.
In order to guarantee correctness of simulations, conventional parallel Discrete Event simulation models impose a sequential mode of execution on the events belonging to a logical process (LP). This constraint, which ...
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A great deal of research in the area of distributed discrete event simulation has focussed on evaluating the performance of variants of conservative and optimistic methods on different types of applications. Applicati...
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ISBN:
(纸本)1565550277
A great deal of research in the area of distributed discrete event simulation has focussed on evaluating the performance of variants of conservative and optimistic methods on different types of applications. Application characteristics like lookahead, communication patterns, etc. have been found to affect the suitability of a specific protocol to simulate a given model. For many systems, it may be the case that different subsystems possess contradictory characteristics such that whereas some subsystems may be simulated efficiently using a conservative protocol, others may be more amenable to optimistic methods. Furthermore, the suitability of a protocol for a given subsystem may change dynamically. We propose a parallelsimulation protocol that allows different parts of a system to be simulated using different protocols, allowing these protocols to be switched dynamically. A proof of correctness is presented, along with some preliminary performance discussion.
One of the significant difficulties in partitioning logic circuits for distributedsimulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researche...
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ISBN:
(纸本)1565550277
One of the significant difficulties in partitioning logic circuits for distributedsimulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researchers have resorted to pre-simulation to estimate these evaluation frequencies. In this paper we empirically investigate the wisdom of relying on presimulation results, and evaluate the degree to which early evaluation frequencies predict later evaluation frequencies. The results show that, for simulations that use random input vectors, pre-simulation has clear merit in predicting circuit element evaluation frequency. This supports the use of pre-simulation as an input to circuit partitioning algorithms.
A parallel implementation of the numerical simulation of a GaAs MESFET device based on the energy transport model using the finite difference discretization scheme and solved by a point iterative method is presented. ...
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This paper describes a tool, LAPSE (Large Application parallelsimulation Environment), that allows one to use a small number of parallel processors to simulate the behavior of a message-passing code running on a larg...
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ISBN:
(纸本)1565550277
This paper describes a tool, LAPSE (Large Application parallelsimulation Environment), that allows one to use a small number of parallel processors to simulate the behavior of a message-passing code running on a large number of processors, for the purposes of scalability studies and performance tuning. LAPSE is implemented on the Intel Paragon, and has achieved small slowdowns (relative to native code) and high speed-ups on large problems.
Generalized proximity detection for moving objects in a logically correct parallel discrete-event simulation is an interesting and fundamentally challenging problem. Determining who can see whom in a manner that is fu...
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ISBN:
(纸本)1565550277
Generalized proximity detection for moving objects in a logically correct parallel discrete-event simulation is an interesting and fundamentally challenging problem. Determining who can see whom in a manner that is fully scalable in terms of CPU usage, number of messages, and memory requirements is highly non-trivial. A new scalable approach has been developed to solve this problem. This algorithm, called The Distribution List, has been designed and tested using the object-oriented Synchronous parallel Environment for Emulation and Discrete-Event simulation (SPEEDES) operating system. Preliminary results show that The Distribution List algorithm achieves excellent parallel performance.
IVD, Interactive Visualization Debugger, is intended to provide on-line and integrated mechanisms for debugging, performance analysis, and data visualization for message-passing parallel applications. The current IVD ...
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ISBN:
(纸本)0818652926
IVD, Interactive Visualization Debugger, is intended to provide on-line and integrated mechanisms for debugging, performance analysis, and data visualization for message-passing parallel applications. The current IVD includes: (1) ESP, a mechanism to multicast window-based commands from a single control window to some subset of existing debuggers/visualizers on various processes;(2) program replay to reproduce program runs deterministically to enable cyclic debugging;and (3) ad hoc data visualization of distributed arrays using existing visualizers.
Fast, efficient parallel algorithms are presented for discrete event simulations of dynamic channel assignment schemes for wireless cellular communication networks. The driving events are call arrivals and departures,...
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ISBN:
(纸本)1565550277
Fast, efficient parallel algorithms are presented for discrete event simulations of dynamic channel assignment schemes for wireless cellular communication networks. The driving events are call arrivals and departures, in continuous time, to cells geographically distributed across the service area. A dynamic channel assignment scheme decides which call arrivals to accept, and which channels to allocate to the accepted calls, attempting to minimize call blocking while ensuring co-channel interference is tolerably low. Specifically, the scheme ensures that the same channel is used concurrently at different cells only if the pairwise distances between those cells are sufficiently large. Much of the complexity of the system comes from ensuring this separation. The network is modeled as a system of interacting continuous time automata, each corresponding to a cell. To simulate the model, we use conservative methods;i.e., methods in which no errors occur in the course of the simulation and so no rollback or relaxation is needed. Implemented on a 16K processor MasPar MP-1, an elegant and simple technique provides speedups of about I5x over an optimized serial simulation running on a high speed workstation. A drawback of this technique, typical of conservative methods, is that processor utilization is rather low. To overcome this, we developed new methods that exploit slackness in event dependencies over short intervals of time, thereby raising the utilization to above 50% and the speedup over the optimized serial code to about 120x with respect to the workstation simulation.
The performance risks of parallel software development have been shown to cause large escalations in project costs. This paper explains how the VPB performance tools developed by CRL can be used to control such risks....
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