This paper presents the results of an experimental study to evaluate the effectiveness of parallelsimulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper ...
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This paper presents the results of an experimental study to evaluate the effectiveness of parallelsimulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols);in particular we showed that a speedup of about 3 was obtained on 8 processors of a Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite;and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.
In a distributed memory environment the communication overhead of Time Warp is the dominating performance factor. In order to limit the optimism to the extent that can be justified from the inherent model parallelism,...
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In a distributed memory environment the communication overhead of Time Warp is the dominating performance factor. In order to limit the optimism to the extent that can be justified from the inherent model parallelism, an optimism control mechanism is proposed. After investigating statistical forecast methods, it is shown that arrival processes in the context of Time Warp simulations of timed Petri nets have certain predictable and consistent ARIMA characteristics.
The implementation of a distributed digital logic simulation algorithm on a network of workstations is presented. The simulation of digital circuits is done using a demand driven approach. The simulation is performed ...
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Performance of Time Warp simulation systems are often measured on exclusively available parallel computing resources. In distributed systems exclusive use is normally not feasible. Instead, due to the multi-tasking op...
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Performance of Time Warp simulation systems are often measured on exclusively available parallel computing resources. In distributed systems exclusive use is normally not feasible. Instead, due to the multi-tasking operating systems, many users share the workstations and their availability for parallelsimulation purposes varies extensively. Time Warp has been found to be very sensitive to variations in available processing power. This paper presents two methods for a Time Warp VLSI simulation system to reduce the negative effect of a non-ideal environment on the execution of parallelsimulations. A dynamic load balancing algorithm which adapts to the change of available processing power is presented. This mechanism, together with a multi-cluster partitioning technique significantly improves the performance of Time Warp based simulation systems on heterogeneous computing resources.
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