This paper describes a modeling project which was established to support the design of a distributed controller system. An anthropomorphic robot hand is the target system. Stochastic Petri net models for different com...
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Conformance testing of communication protocols has recently become a major issue in the context ofOSI-based standardization of protocols. The aim of conformance testing is to assure that a protocol fulfills an OSI spe...
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In a distributed real-time system, tolerance to faults on processing nodes in the system is achieved by means of redundant nodes and a fault-tolerant scheduling algorithm. Since redundant nodes increase total failure ...
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This paper discusses the algorithms for numerical simulation of semuconductor devices (in particular using quasi-hydrodynamic model) on multiprocessor computer systems with distributed memory. parallel implementation ...
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We propose a new process scheduling queue system called the distributed queue tree (DQT) for a distributed memory, dynamically partitionable parallel machines. We assume that partitions can be nested dynamically and t...
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A new technique for the efficient asynchronous discrete event-driven simulation of parallel shared-memory computers is proposed. Our execution-driven methodology, while introducing minimal synchronization overhead to ...
This paper presents a performance comparison of real-time system architectures. A discrete event-driven, task-based simulator is developed for evaluating the performance of parallel and distributed real-time systems. ...
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This paper presents a performance comparison of real-time system architectures. A discrete event-driven, task-based simulator is developed for evaluating the performance of parallel and distributed real-time systems. Real-time system components such as processor, network architectures, and scheduling policy are included in the simulator. simulation results show that priority-based communication and scheduling are more suitable for real-time systems than FIFO-based. The strategy of having a dedicated processor, which produces no effect on task execution by scheduling and packet/interrupt handling, is proven to enhance schedulability and predictability. This paper suggests a method for finding an appropriate real-time architecture for users having real-time requirements through the performance prediction of real-time systems.
Research into DBMS (Database Management System) parallelism has been carried out to address the performance problems experienced in areas such as Decision Support. distributed shared memory can alleviate the porting o...
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VIZIR provides an integrated mechanism for on-line debugging, performance analysis, and data visualization of message-passing parallel applications. The current VIZIR includes: (1) a mechanism to multicast window-base...
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The proceedings contain 38 papers. The special focus in this conference is on Fine Grain parallelism I and Interprocedural Analysis. The topics include: Array data flow analysis for load-store optimizations in supersc...
ISBN:
(纸本)9783540607656
The proceedings contain 38 papers. The special focus in this conference is on Fine Grain parallelism I and Interprocedural Analysis. The topics include: Array data flow analysis for load-store optimizations in superscalar architectures;an experimental study of an ILP-based exact solution method for software pipelining;an alternative to list scheduling for modulo schedulers;interprocedural array region analyses;interprocedural analysis for parallelization;interprocedural array data-flow analysis for cache coherence;an interprocedural parallelizing compiler and its support for memory hierarchy research;a calculus for the compilation of data parallel languages;transitive closure of infinite graphs and its applications;demand-driven, symbolic range propagation;optimizing fortran 90 shift operations on distributed-memory multicomputers;a loop parallelization algorithm for HPF compilers;fast address sequence generation for data-parallel programs using integer lattices;compiling array statements for efficient execution on distributed-memory machines;a communication backend for parallel language compilers;parallelsimulation of data parallel programs;a parallel processing support library based on synchronized aggregate communication;a MATLAB interactive restructuring compiler;a simple mechanism for improving the accuracy and efficiency of instruction-level disambiguation;improving super-scalar processor performance;integer loop code generation for VLIW;piecewise execution of nested data-parallel programs;recovering logical structures of data;efficient distribution analysis via graph contraction;automatic selection of dynamic data partitioning schemes for distributed-memory multicomputers;data redistribution in an automatic data distribution tool and general purpose optimization technology.
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