The two main approaches to parallel discrete event simulation – conservative and optimistic – are likely to encounter some limitations when the size and complexity of the simulation system increases. For such large ...
ISBN:
(纸本)9781565550551
The two main approaches to parallel discrete event simulation – conservative and optimistic – are likely to encounter some limitations when the size and complexity of the simulation system increases. For such large scale simulations, the conservative approach appears to be limited by blocking overhead and sensitivity to lookahead, whereas the optimistic approach may become prone to cascading rollbacks, state saving overhead, and demands for larger memory space. These drawbacks restrict the synchronization schemes based on each of the two approaches from scaling up. A combined approach may resolve these limitations, while preserving and utilizing potential advantages of each method. However, the schemes proposed so far integrate the two views at the same level, i.e. local to a logical process, and hence may not be able to fully solve the problems. In this paper we propose the Local Time Warp method for parallel discrete-event simulation and present a novel synchronization scheme for it called HCTW. The new scheme hierarchically combines a Conservative Time Window algorithm with Time Warp and aims at reducing cascade rollbacks, sensitivity to lookahead, and the scalability problems. Local Time Warp is believed to be suitable for parallel machines equipped with thousands of processors and thus an appropriate candidate for simulation of large and complex systems.
A hardware-based framework which supports a wide range of parallel discrete event synchronization protocols has been proposed in [Reyn92]. This framework offloads all synchronization activity from the host processors ...
ISBN:
(纸本)9781565550551
A hardware-based framework which supports a wide range of parallel discrete event synchronization protocols has been proposed in [Reyn92]. This framework offloads all synchronization activity from the host processors and host communication network in the system. The underlying hardware computes results of global, binary associative operations, or global reductions. In this paper we present results of simulations that strongly suggest the need for a next-generation reduction network which computes and disseminates results of target-specific reductions to support both aggressive and non-aggressive parallel discrete event simulations. Target-specific reductions allow a logical process to receive synchronization information only from those logical processes which may have a direct or indirect impact on its performance.
In this paper, a modular neurocontroller for an arbitrary N-DOF (degree of freedom) manipulator is proposed. The recursive nature of the Newton-Euler formulation is used as a base for the modular neurocontroller. The ...
详细信息
In this paper, a modular neurocontroller for an arbitrary N-DOF (degree of freedom) manipulator is proposed. The recursive nature of the Newton-Euler formulation is used as a base for the modular neurocontroller. The neural modules can be trained by the direct inverse or indirect adaptive control schemes. Computer simulation results for a 2-DOF SCARA manipulator are given. Due to its modular structure, this neurocontroller can be applied to a manipulator with arbitrary degrees of freedom such as distributed or cellular robotic systems.
Assembly task planning for multiple robots is highly complicated and cumbersome. A new assembly task planning system for multiple robots is proposed to avoid this problem and to improve the flexibility and the reliabi...
详细信息
Assembly task planning for multiple robots is highly complicated and cumbersome. A new assembly task planning system for multiple robots is proposed to avoid this problem and to improve the flexibility and the reliability in assembly tasks. In this system, parts with which a machine is composed are handled as part-objects and plans for assembling the machine are automatically generated as results of autonomous behaviors of these objects. The outline of the planning system, based on this concept is described. Some simulation results using a cooperative computational model are given.< >
The suitability of the Time Warp mechanism to perform simulations with real-time constraints is examined. A model for Time Warp is developed that accounts for overheads such as state saving, state restoration, and sen...
ISBN:
(纸本)9781565550551
The suitability of the Time Warp mechanism to perform simulations with real-time constraints is examined. A model for Time Warp is developed that accounts for overheads such as state saving, state restoration, and sending and transmitting positive and negative messages. A criterion called R-schedulability is defined to indicate whether or not computations can meet real-time deadlines. It is shown that if false events (events that will be rolled back or cancelled later) are generated, and there are no committed events with timestamps equal to those of the false events, Time Warp cannot meet the R-schedulability criterion. Further, if aggressive cancellation is used, scheduling guarantees still cannot be made even in the absence of such false events. However, Time Warp using lazy cancellation is shown to be R-schedulable provided such false events do not exist. Finally, based on these results, bounds on the execution time of a Time Warp simulation are derived.
This paper describes a parallel computer architecture for real-time image synthesis. Our architecture is based on a loosely-coupled array of general-purpose processors equipped with a novel frame buffer sub-system cal...
详细信息
ISBN:
(纸本)0818627557
This paper describes a parallel computer architecture for real-time image synthesis. Our architecture is based on a loosely-coupled array of general-purpose processors equipped with a novel frame buffer sub-system called a conflict-free multiport frame buffer (CFMFB) which enables every processor to write any region of the screen without access conflicts. An efficient polygon rendering method using the CFMFB is also described. The method assigns a subset of the polygons to each processor, which independently calculates the images of the assigned polygons with the Z-buffer algorithm. The performance of our system is estimated through simulation experiments with sample scenes.
This paper describes a parallel computer architecture for real-time image synthesis. The architecture is based on a loosely-coupled array of general purpose processors equipped with a novel frame buffer subsystem call...
详细信息
This paper describes a parallel computer architecture for real-time image synthesis. The architecture is based on a loosely-coupled array of general purpose processors equipped with a novel frame buffer subsystem called a conflict-free multiport frame buffer (CFMFB) which enables every processor to write any region of the screen without access conflicts. An efficient polygon rendering method using the CFMFB is also described. The method assigns a subset of the polygons to each processor, which independently calculates the images of the assigned polygons with the Z-buffer algorithm. The performance of the system is estimated through simulation experiments with sample scenes.< >
Software prototyping is one approach which may be used early on in the software lifecycle to analyze and validate software requirements. parallel Proto is a software prototyping tool for analyzing and validating funct...
详细信息
暂无评论