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proceedings of the Fourth IEEE International workshop on distributed simulation and Real-Time Applications

作者： Judd Tracy Ravishankar Palaniappan

ISBN: (纸本)9780769508375

In this paper, we examine various modeling and simulation applications of cluster computing using a Beowulf cluster. These applications are used to investigate the performance of our cluster in terms of computational speedup, scalability, and communications. The applications include solution of linear systems by Jacobi iteration, distributed image generation, and the finite difference time domain solution of Maxwell's equations. It is observed that the computational load for these applications must be large compared to the communication overhead to take advantage of the speedup obtained using parallel computing. For the applications reviewed here, this condition is increasingly satisfied as the problem size becomes larger or as higher resolution is required.

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Strategies for success in parallel simulation applications (keynote speech) 00

Strategies for success in parallel simulation applications (...

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proceedings of the fourteenth workshop on parallel and distributed simulation

作者： Frederick Wieland The MITRE Corporation Center for Advanced Aviation Systems Development McLean VA

ISBN: (纸本)9780769506678

While the PADS community has traditionally focused on—and done a greater job with—the technical aspects of developing simulations that run fast and can be connected to other simulations, it has paid little or no attention to the overall strategies required to produce a marketable, useful, and successful parallel simulation. This lack of market focus has led to many fears of the demise of the PADS community, complaints of its lack of general acceptance by the broader simulation community, and predictions that it will become merely another venue for simulation *** fears, complaints, and predictions are unnecessary. There are several examples of successful parallel simulations—in domains as far apart as aviation modeling and wargames. What can we learn from their successes? How can we translate their general acceptance into other parallel simulation domains? Are there market opportunities that we are missing? In short, what is the parallel simulation community lacking, and what does it need to do in order to be more successful?The purpose of this talk is to begin a discussion on the answers to these questions (as opposed to definitively answering them). We will draw on numerous examples of successful applications, and make some concrete suggestions for furthering the community.

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parallel mixed-technology simulation 00

Parallel mixed-technology simulation

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proceedings of the fourteenth workshop on parallel and distributed simulation

作者： Peter Frey Radharamanan Radhakrishnan Cadence Design Systems 2655 Seely Avenue San Jose CA Dept. of ECECS University of Cincinnati Cincinnati OH

ISBN: (纸本)9780769506678

Circuit simulation has proven to be one of the most important computer aided design (CAD) methods for the analysis and validation of integrated circuit designs. A popular approach to describing circuits for simulation purposes is to use a hardware description language such as VHDL. Similar efforts have also been carried out in the analog domain that has led to tools such as SPICE. However, with the growing trend of hardware designs that contain both analog and digital components, design environments that seamlessly integrate analog and digital circuitry are needed. simulation of such circuit is however, exacerbated by the higher resource (CPU and memory) demands that arise when analog and digital models are integrated in a mixed-mode (analog and digital) simulation. One solution to this problem is to use PDES algorithms on a distributed platform. However, a synchronization interface between the analog and digital simulation environment is required to achieve integrated mixed-mode simulation. In this paper, we present the issues involved in the construction of synchronization protocols which support mixed-mode simulation in a distributed simulation environment. The proposed synchronization protocols provide an interface between an optimistic (Time Warp based) discrete-event simulation kernel and any continuous time simulation kernel. Empirical and formal analyses were conducted to ensure correctness and completeness of the protocols and the results of these analyses are also presented.

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Application-aware scheduling of a magnetohydrodynamics application in the legion metasystem

Proceedings of the Heterogeneous Computing Workshop, HCW

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proceedings of the Heterogeneous Computing workshop, HCW 2000年 216-228页

作者： Dail, Holly Obertelli, Graziano Berman, Francine Wolski, Rich Grimshaw, Andrew Univ of California San Diego San Diego United States

Computational Grids have become an important and popular computing platform for both scientific and commercial distributed computing communities. However, users of such systems typically find achievement of application execution performance remains challenging. Although Grid infrastructures such as Legion and Globus provide basic resource selection functionality, work allocation functionality, and scheduling mechanisms, applications must interpret system performance information in terms of their own requirements in order to develop performance-efficient schedules. We describe a new high-performance scheduler that incorporates dynamic system information, application requirements, and a detailed performance model in order to create performance efficient schedules. While the scheduler is designed to provide improved performance for a magneto hydrodynamics simulation in the Legion Computational Grid infrastructure, the design is generalizable to other systems and other data-parallel, iterative codes. We describe the adaptive performance model, resource selection strategies, and scheduling policies employed by the scheduler. We demonstrate the improvement in application performance achieved by the scheduler in dedicated and shared Legion environments.

关键词： distributed computer systems

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Optimizing cell-size in grid-based DDM 00

Optimizing cell-size in grid-based DDM

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proceedings of the fourteenth workshop on parallel and distributed simulation

作者： Rassul Ayani Farshad Moradi Gary Tan School of Computing National University of Singapore Singapore 119260

ISBN: (纸本)9780769506678

In a large-scale distributed simulation with thousands of dynamic objects, efficient communication of data among these objects is an important issue. The broadcasting mechanism specified by the distributed Interactive simulation (DIS) standards is not suitable for large scale distributed *** the High Level Architecture (HLA) paradigm, the Runtime Infrastructure (RTI) provides a set of services, such as data distribution management (DDM) among federates. The goal of the DDM module in RTI is to make the data communication more efficient by sending the data only to those federates that need the data, as opposed to the broadcasting mechanism employed by *** DDM schemes have appeared in the literature. In this paper, we discuss grid-based DDM and develop a DDM model that uses grids for matching the publishing/subscription regions, and for data filtering. We show that appropriate choice of the grid-cell size is crucial in obtaining good performance. We develop an analytical model and derive a formula for identifying the optimal cell size in grid-based DDM.

关键词： HLA group communication distributed simulation data filtering data communication

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parallelizing a sequential logic simulator using an optimistic framework based on a global parallel heap event queue: an experience and performance report 00

Parallelizing a sequential logic simulator using an optimist...

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proceedings of the fourteenth workshop on parallel and distributed simulation

作者： Sushil K. Prasad Nikhil Junankar Computer Science Department Georgia State University Atlanta

ISBN: (纸本)9780769506678

We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.

关键词： parallel heap parallel discrete event simulation parallelizing framework logic simulation

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Load balancing for conservative simulation on shared memory multiprocessor systems 00

Load balancing for conservative simulation on shared memory ...

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proceedings of the fourteenth workshop on parallel and distributed simulation

作者： Boon Ping Gan Yoke Hean Low Sanjay Jain Stephen J. Turner Wentong Cai Wen Jing Hsu Shell Ying Huang Gintic Institute of Manufacturing Technology 71 Nanyang Drive Singapore 638075 School of Applied Science Nanyang Technological University Nanyang Avenue Singapore 639798

ISBN: (纸本)9780769506678

Load balancing is a crucial factor in achieving good performance for parallel discrete event simulations. In this paper, we present a load balancing scheme that combines both static partitioning and dynamic load balancing. The static partitioning scheme maps simulation objects to logical processes before simulation starts while the dynamic load balancing scheme attempt to balance the load during runtime. The static scheme involves two steps. First, the simulation objects that contribute to small lookahead are merged together by using a merging algorithm. Then a partitioning algorithm is applied. The merging is needed to ensure a consistent performance for our dynamic scheme. Our dynamic scheme is tailor-made for an asynchronous simulation protocol that does not rely on null messages. The performance study on a supply-chain simulation shows that the partitioning algorithm and dynamic load balancing are important in achieving good performance.

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Structural modeling for simulation of power electronic systems

Structural modeling for simulation of power electronic syste...

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IEEE workshop on Computers in Power Electronics

作者： V.P. Guzik V.E. Zolotovsky Yu.V. Chemukhin S.V. Tretyakov O.A. Muntyan R.A. Dougal Taganrog State Univ. of Radio-Eng. Russia Taganrog State University of Radio Engineering Taganrog Russia University of South Carolina Columbia SC USA

ISBN: (纸本)0780365615

Power electronic systems are described by nonlinear differential equations, typically of high order. simulation of such systems increasingly requires the high speeds available only on multiprocessor computing systems. However, the traditional methods for partitioning the system are rather inconvenient, primarily because of the additional burden created by the current operation associated with distributed systems. The concepts and methods of structural modeling provide a way to overcome this difficulty. The essence of structural modeling is the assignment of some specific computing resource to each object of the simulated physical system. The simulation of each object then operates as a formal independent procedure, and interactions between objects are implemented on a data link level. This allows parallel execution of the separate procedures on the allocated multiprocessor computing hardware. This provides two advantages: (1) a decrease in simulation time, and (2) simplification of the programming process.

关键词： Power system modeling Computational modeling Circuit simulation Power electronics Differential equations Multiprocessing systems Power system interconnection Power system simulation Libraries Physics computing

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Quantum neurocomputation and signal processing

Quantum neurocomputation and signal processing

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IEEE workshop on Neural Networks for Signal Processing

作者： H. Eghbalnia A. Assadi University of Wisconsin Madison USA

We consider a quantum computational algorithm that can be used to determine (probabilistically) how close a given signal is to one of a set of previously observed signals stored in the state of a quantum neurocomputional machine. The realization of a new quantum algorithm for factorization of integers by Shor and its implication to cryptography has created a rapidly growing field of investigation. Although no physical realization of a quantum computer is available, a number of software systems simulating a quantum computation process exist. In light of the rapidly increasing power of desktop computers and their ability to carry out these simulations, it is worthwhile to investigate possible advantages as well as realizations of quantum algorithms in signal processing applications. The algorithm presented offers a glimpse of the potential of this approach. Neural networks (NN) provide a natural paradigm for parallel and distributed processing of a wide class of signals. Neural networks within the context of classical computation have been used for approximation and classification tasks with some success. We propose a model for quantum neurocomputation (QN) and explore some of its properties and potential applications to signal processing in an information theoretic context.

关键词： Signal processing Quantum computing Signal processing algorithms Neural networks Physics computing Computational modeling Computer simulation Cryptography Software systems Application software

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A special purpose hybrid SIMD processor for logic event simulation 7

A special purpose hybrid SIMD processor for logic event simu...

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7th Euromicro workshop on parallel and distributed Processing (PDP 99)

作者： Dalton, D Natl Univ Ireland Univ Coll Dublin Dept Comp Sci Dublin 4 Ireland

ISBN: (纸本)0769500595

This paper introduces a hybrid Associative memory/SIMD parallel processor, APPLES, which has been specifically designed for logic simulation. Its reviews the computational structure which permits parallel execution of logic gate evaluations in memory. This facilitates fine grain execution on a massive scale of the basic tasks inherent in VLSI logic simulation. Furthermore, unlike of her SIMD approaches the simulation is not limited to a unit delay model, complex delays such as inertial delays are permissible. The processor has been implemented in Verilog and assessed using ISCAS-85 benchmarks. Gate evaluation is executed in constant time, whereas updating fan-out lists expands with circuit size. However, the APPLES architecture enables this latter task to be parallelised subject to various system parameters. The most important constraint is identified as the fan-out memory access time relative to the scan rate of the associative memory.

关键词： Discrete event simulation Computational modeling Delay Associative memory Circuit simulation Logic design Concurrent computing Logic gates Very large scale integration Hardware design languages

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