This paper describes a database approach to parallel discrete event simulation. It employs a set of production rules to describe the behavior of active objects in a simulation system so that production rules can be me...
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This paper describes a database approach to parallel discrete event simulation. It employs a set of production rules to describe the behavior of active objects in a simulation system so that production rules can be merged and evaluated collectively in a rule network. To maintain correctness and exploit all possible parallelism, each token is time-stamped and can be processed asynchronously. An object relational database is employed to allow simulators located at different sites of an Intranet to communicate with each other. A dynamic, object-relational query tool is provided for the user to interact with the simulation system.
The problem of testing digital circuits is becoming much more difficult as these circuits increase in size and complexity. Thus, the development of parallel procedures for test pattern generation is currently a field ...
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The problem of testing digital circuits is becoming much more difficult as these circuits increase in size and complexity. Thus, the development of parallel procedures for test pattern generation is currently a field of important research activity. A new parallel procedure to determine the set of patterns to test a circuit is presented. It stems from a circuit partitioning scheme based on a mixed simulated annealing and tabu search technique which allows the load to be distributed among the processors in such a way that similar sized parts of the circuit are assigned to each processor while communications between processors are minimised. The method applied by each processor to obtain the test pattern uses an algorithm based on the Reed-Muller spectrum to determine the equation, thus being different from other procedures previously reported. The experimental results obtained by applying the procedure to the usual benchmark circuits in this field (ISCAS set) show good efficiencies which are maintained when the number of processors increases.
In the last years, since the early 80's, wormhole and virtual cut through routing modalities have replaced packet switching and circuit switching schemes. We give the theoretical bases to implement hole based (HB)...
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In the last years, since the early 80's, wormhole and virtual cut through routing modalities have replaced packet switching and circuit switching schemes. We give the theoretical bases to implement hole based (HB) routing algorithm (M. Coli and P. Palazzari, 1995) by using the virtual cut through modality. After reviewing the theory of HB routing, we demonstrate some theorems which allow us to use such a theory, developed for the packet switching case, also for the virtual cut through modality (HB-VCT routing algorithm). The main features of HB-VCT are its full adaptivity, the high fault tolerance capabilities and the low HW requirement. Furthermore, low latencies and high bandwidths are achievable because the use of virtual channels can be avoided. Some simulated results are presented in order to show the good traffic balance capabilities and the fault tolerant behavior of HB-VCT. simulation is also used to show the influence on throughput of traffic intensity and of a HB-VCT control parameter (the timeout).
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