We present a low cost efficient multimicroprocessor designed to study parallel algorithms like fixed point parallel algorithms or parallel algorithms for distributed systems control. This multiprocessor is a collectio...
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ISBN:
(纸本)0306424096
We present a low cost efficient multimicroprocessor designed to study parallel algorithms like fixed point parallel algorithms or parallel algorithms for distributed systems control. This multiprocessor is a collection of 8 processors sharing a common memory. Its architecture presents some original features that guarantee data consistency and good efficiency. Experimental results are given for synchronous and asynchronous algorithms applied to the Dirichlet problem.
The practical implementation of an integrated system optimization and parameter estimation technique for hierarchical control of steady state systems has been investigated using a distributed hierarchical computer sys...
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ISBN:
(纸本)0306424096
The practical implementation of an integrated system optimization and parameter estimation technique for hierarchical control of steady state systems has been investigated using a distributed hierarchical computer system. Problems associated with the on-line implementation of the technique have been discussed and methods for dealing with these problems are suggested and have been tested in the real-time situation. It is demonstrated that a double iterative version of the technique has important advantages under real time operation.
The systolic architecture concept has become widely popular in the design of VLSI special purpose architectures for applications like signal processing, image processing, etc. To make this architecture design simple a...
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ISBN:
(纸本)0444701044
The systolic architecture concept has become widely popular in the design of VLSI special purpose architectures for applications like signal processing, image processing, etc. To make this architecture design simple and attractive, inexpensive computer aided design tools have to be developed. Towards this step, two computer aided design systems namely DIASTOL and MISS are developed at IRISA, Rennes, France. This paper describes the system MISS Machine for Systolic simulation, which is a distributedsimulation system implemented on a dedicated multi-microprocessor architecture.
simulations are among the most expensive of computational tasks. Consequently, different authors [PEAC79], [CHAN81], [JEFF82] have investigated methods for performing fast concurrent simulations on a netwprk of proces...
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ISBN:
(纸本)9781450373357
simulations are among the most expensive of computational tasks. Consequently, different authors [PEAC79], [CHAN81], [JEFF82] have investigated methods for performing fast concurrent simulations on a netwprk of processors. Basic issues are synchronization (events must be simulated in the order in which, they are executed in the real system), flow control and memory management. There are two basic groups of synchronization algorithms, the blocking algorithms [PEAC79], [CHAN79], [CHAN81] and the Time Warp mechanism [JEFF82]. In blocking algorithms, the simulated system Is represented as a network of logical processes (LP's) or objects and directed links representing communication channels between the objects. Each LP simulates a physical process (PP) in the real system. LP's communicate by exchanging timestamped event messages. An LP is allowed to execute an event with the timestamp t if it is sure it will not receive an event with the timestamp smaller than t in the future. Thus, events are always executed in monotonically Increasing time order. This implies that the output times-tamps are in an increasing time order as well. Assuming that the communication medium preserves the order of messages, they arrive on a particular input link in an Increasing time order. An input buffer is assigned to each input link. This mechanism implies that an LP can always execute the input event with the smallest times-' tamp if each of the input buffers contains at least one event message. In the event that one or more input quaues are empty, the LP is blocked because an event with a timestamp smaller than the timestamps of the waiting events, might yet arrive via an empty input link. Therefore all LP's in the system can be divided at any time into two groups- blocked and unblocked. Only unblocked LP's can execute in parallel (Fig. 1). If all LP's were blocked the simulation would deadlock. This type of the deadlock may occur even when we assume unlimited buffering at the LP's. With
This book constitutes the thoroughly refereed post-conference proceedings of the 18th International workshop on Job Scheduling Strategies for parallel Processing, JSSPP 2014, held in Phoenix, AZ, USA, in May 2014. The...
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ISBN:
(数字)9783319157894
ISBN:
(纸本)9783319157887
This book constitutes the thoroughly refereed post-conference proceedings of the 18th International workshop on Job Scheduling Strategies for parallel Processing, JSSPP 2014, held in Phoenix, AZ, USA, in May 2014. The 9 revised full papers presented were carefully reviewed and selected from 24 submissions. The papers cover the following topics: single-core parallelism; moving to distributed-memory, larger-scale systems, scheduling fairness; and parallel job scheduling.
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