the proceedings contains 86 papers. Topics discussed include algorithms, parallelprocessing systems, program processors, computer software, genetic algorithms, optimization, computer architecture, data structures, di...
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the proceedings contains 86 papers. Topics discussed include algorithms, parallelprocessing systems, program processors, computer software, genetic algorithms, optimization, computer architecture, data structures, distributed computer systems, network protocols, state estimation, program debugging, large scale systems and data communication systems.
We propose a new family of trivalent network graphs with constant node degree 3 for design of massively parallel systems. these graphs are shown to be regular, to have logarithmic diameter in the number of nodes, and ...
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We propose a new family of trivalent network graphs with constant node degree 3 for design of massively parallel systems. these graphs are shown to be regular, to have logarithmic diameter in the number of nodes, and to be maximally fault tolerant. We investigate different algebraic properties of these networks (including fault tolerance) and propose simple and optimal routing algorithms. We also show that the proposed graph belongs to the well known family of Cayley graphs.
In multicomputers, an appropriate data distribution is crucial for reducing communication overhead and therefore the overall performance. For this reason, data parallel languages provide programmers with primitives, s...
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In multicomputers, an appropriate data distribution is crucial for reducing communication overhead and therefore the overall performance. For this reason, data parallel languages provide programmers with primitives, such as BLOCK and CYCLIC that can be used to distribute data across the distributed memory. However, the languages do not aid the programmer as to how the distribution should be performed to maximize the performance. therefore, this paper presents an analysis of data distribution methods for overlapping computation and communication in the Gaussian elimination algorithm. the analysis indicates that both BLOCK and CYCLIC distributions have their own merit;however, BLOCK_CYCLIC with its hybrid characteristic consistently out performs its counterparts.
We discuss a style of designing parallel algorithms withthe following characteristics for a problem of the best known sequential time T(n): C1. Each processor spends O(T(n)÷P) time in computing. C2. Each process...
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We discuss a style of designing parallel algorithms withthe following characteristics for a problem of the best known sequential time T(n): C1. Each processor spends O(T(n)÷P) time in computing. C2. Each processor sends and/or receives O(n÷P) messages of one-word-size. C3. the number of communication phases is constant, independent of the input size n. We show this is possible to achieve for several fundamental computational problems.
Most studies of processor scheduling in multiprogrammed parallel systems have ignored the I/O performed by applications. Recent studies have demonstrated that significant I/O operations are performed by a number of di...
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Most studies of processor scheduling in multiprogrammed parallel systems have ignored the I/O performed by applications. Recent studies have demonstrated that significant I/O operations are performed by a number of different classes of parallel applications. this paper focuses on some basic issues that underlie scheduling in multiprogrammed parallel environments running applications with I/O. Characterization of the I/O behavior of parallel applications is discussed first. Based on simulation models this research investigates the influence of these I/O characteristics on processor scheduling.
A renegable priority queue has been designed on two different types of network. the first design uses hypercube networks, and has a response time and a pipeline cycle time O(log p), where p is the maximum number of pr...
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A renegable priority queue has been designed on two different types of network. the first design uses hypercube networks, and has a response time and a pipeline cycle time O(log p), where p is the maximum number of processors that may access the design simultaneously. the second design uses reconfigurable meshes with both response time and pipeline cycle time being constants. Each of these designs uses O(p2m) processing elements, and have a capacity of pm, where m is a positive integer.
there are several models that were proposed in recent years for message passing parallel systems. Examples are the postal model and its generalization the LogP model. In the postal model, a parameter λ is used to mod...
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there are several models that were proposed in recent years for message passing parallel systems. Examples are the postal model and its generalization the LogP model. In the postal model, a parameter λ is used to model the communication latency of the message passing system. In this paper, the gap between the theoritical modeling and the practical implementation is bridged. In particular, a number of practical issues related to the design and implementation of two collective communication operations, namely, the broadcast operation and the global marine operation is investigated. Results of the investigation are presented.
the utilization of networked, shared, heterogeneous workstations as an inexpensive parallel computational platform is an appealing idea. However, most performance models for parallel computation are oriented towards t...
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the utilization of networked, shared, heterogeneous workstations as an inexpensive parallel computational platform is an appealing idea. However, most performance models for parallel computation are oriented towards the use of tightly-coupled, dedicated, homogeneous processors. We develop and validate an analytic performance model for synchronous iterative algorithms executing on networked workstations. the model includes the effects of application load, background load, and processor heterogeneity. the model is validated using a pair of applications: a nonlinear optimization code and discrete-event simulation.
the virtual computers (VC) paradigm enables the incorporation of predictability and choice into the design of an operating system. Predictability refers to the ability of the system to provide each user with a computi...
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the virtual computers (VC) paradigm enables the incorporation of predictability and choice into the design of an operating system. Predictability refers to the ability of the system to provide each user with a computing environment whose performance is independent of the behavior of other users. Choice refers to the ability of a user to select a computer system that meets that user's specifications, needs or budget. In this paper, we introduce this new paradigm and show how the VC paradigm can be incorporated into the processor scheduling, and how the on-line schedulers can be effectively implemented.
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