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检索条件"任意字段=Proceeedings of the 6th IEEE Symposium on Parallel and Distributed Processing"

共 459 条记录，以下是31-40 订阅

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Evaluating and Improving thread-Level Speculation in Hardware Transactional Memories 30

Evaluating and Improving Thread-Level Speculation in Hardwar...

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Salamanca, Juan Amaral, Jose Nelson Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil Univ Alberta Dept Comp Sci Edmonton AB T6G 2M7 Canada

ISBN: (纸本)9781509021406

this paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them;(b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS;(c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns.

关键词： Hardware Transactional Memory Transactional Memory thread-Level Speculation

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On Competitive Algorithms for Approximations of Top-k-Position Monitoring of distributed Streams 30

On Competitive Algorithms for Approximations of Top-<i>k</i>...

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Maecker, Alexander Malatyali, Manuel Heide, Friedhelm Meyer auf der Univ Paderborn Heinz Nixdorf Inst Paderborn Germany Univ Paderborn Dept Comp Sci Paderborn Germany

ISBN: (纸本)9781509021406

Consider the continuous distributed monitoring model in which n distributed nodes, receiving individual data streams, are connected to a designated server. the server is asked to continuously monitor a function defined over the values observed across all streams while minimizing the communication. We study a variant in which the server is equipped with a broadcast channel and is supposed to keep track of an approximation of the set of nodes currently observing the.. largest values. Such an approximate set is exact except for some imprecision in an epsilon-neighborhood of the k-th largest value. this approximation of the Top-k-Position Monitoring Problem is of interest in cases where marginal changes (e.g. due to noise) in observed values can be ignored so that monitoring an approximation is sufficient and can reduce communication. this paper extends our results from [6], where we have developed a filter-based online algorithm for the (exact) Top-k-Position Monitoring Problem. there we have presented a competitive analysis of our algorithm against an offline adversary that also is restricted to filter-based algorithms. Our new algorithms as well as their analyses use new methods. We analyze their competitiveness against adversaries that use both exact and approximate filter-based algorithms, and observe severe differences between the respective powers of these adversaries.

关键词： Approximation Continuous computation distributed monitoring Online data streams Top-k Tracking

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Block-parallel Data Analysis with DIY2 6

Block-Parallel Data Analysis with DIY2

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6th ieee symposium on Large Data Analysis and Visualization (LDAV)

作者： Morozov, Dmitriy Peterka, Tom Lawrence Berkeley Natl Lab Berkeley CA USA Argonne Natl Lab Argonne IL 60439 USA

ISBN: (纸本)9781509056590

DIY2 is a programming model and runtime for block-parallel analytics on distributed-memory machines. Its main abstraction is block-structured data parallelism: data are decomposed into blocks;blocks are assigned to processing elements (processes or threads);computation is described as iterations over these blocks, and communication between blocks is defined by reusable patterns. By expressing computation in this general form, the DIY2 runtime is free to optimize the movement of blocks between slow and fast memories (disk and flash vs. DRAM) and to concurrently execute blocks residing in memory with multiple threads. this enables the same program to execute in-core, out-of-core, serial, parallel, single-threaded, multithreaded, or combinations thereof. this paper describes the implementation of the main features of the DIY2 programming model and optimizations to improve performance. DIY2 is evaluated on complete analysis codes.

关键词： Computational modeling Runtime Programming Analytical models Message systems Data models Data analysis Runtime Computer based information systems data models Programming ANALYSIS MODELS Computational modeling Data analysis Blocks memory machine

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PTRAM: A parallel Topology- and Routing-Aware Mapping Framework for Large-Scale HPC Systems 30

PTRAM: A Parallel Topology- and Routing-Aware Mapping Framew...

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Mirsadeghi, Seyed H. Afsahi, Ahmad Queens Univ ECE Dept Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781509036820

With the rapid increase in the size and scale of modern systems, topology-aware process mapping has become an important approach for improving system efficiency. A poor placement of processes across compute nodes could cause significant congestion within the interconnect. In this paper, we propose a new greedy mapping heuristic as well as a mapping refinement algorithm. the heuristic attempts to minimize a hybrid metric that we use for evaluating various mappings, whereas the refinement algorithm attempts to reduce maximum congestion directly. Moreover, we take advantage of parallelism in the design and implementation of our proposed algorithms to achieve scalability. We also use the underlying routing information in addition to the topology of the system to derive a better evaluation of congestion. Our experimental results with 4096 processes show that the proposed approach can provide more than 60% improvement in various mapping metrics compared to an initial in-order mapping of processes. Communication time is also improved by 50%. In addition, we also compare our proposed algorithms with 4 other heuristics from the LibTopoMap library, and show that we can achieve better mappings at a significantly lower cost.

关键词： MPI Routing Awareness Topology Mapping

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Topology-Aware Rank Reordering for MPI Collectives 30

Topology-Aware Rank Reordering for MPI Collectives

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Mirsadeghi, Seyed H. Afsahi, Ahmad Queens Univ ECE Dept Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781509036820

As we move toward the Exascale era, HPC systems are becoming more complex, introducing increasing levels of heterogeneity in communication channels. this leads to variations in communication performance at different levels of hierarchy within modern HPC systems. Consequently, communicating peers such as MPI processes should be mapped onto the target cores in a topology-aware fashion so as to avoid message transmissions over slower channels. this is especially true for collective communications due to the global nature of their communication patterns and their vast use in many of parallel applications. In this paper, we exploit the rank reordering mechanism of MPI to realize run-time topology awareness for collective communications and in particular MPI_Allgather. To this end, we propose four fine-tuned mapping heuristics for various communication patterns and algorithms commonly used in MPI_Allgather. the heuristics provide a better match between the collective communication pattern and the topology of the target system. Our experimental results with 4096 processes show that MPI rank reordering using the proposed fine-tuned mapping heuristics can provide up to 78% reduction in MPI_Allgather latency at the micro-benchmark level. At the application level, we can achieve up to 34% reduction in execution time. the results also show that the proposed heuristics significantly outperform the Scotch library which provides a general-purpose graph mapping library.

关键词： Collective Communications Mapping MPI Rank Reordering Topology Awareness

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Mitigating Routing Inefficiencies to Cloud-Storage Providers: A Case Study 30

Mitigating Routing Inefficiencies to Cloud-Storage Providers...

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Sinha, Soham Niu, Di Wang, Zhi Lu, Paul Univ Alberta Dept Comp Sci Edmonton AB T6G 2M7 Canada Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2M7 Canada Tsinghua Univ Grad Sch Shenzhen Beijing Peoples R China

ISBN: (纸本)9781509036820

We provide a case study of current inefficiencies in how traffic to well-known cloud-storage providers (e.g., Dropbox, Google Drive, Microsoft OneDrive) can vary significantly in throughput (e.g., a factor of 5 or more) depending on the location of the source and sink of the data. Our case study supplements previous work on resilient overlay networks (RON) and other ideas. these inefficiencies exist in the presence of vendor-specific points-of-presence (POP), which try to provide better network performance to the clients. In fact, the existence of special-purpose networks (e.g., national research networks, PlanetLab) and complicated peering relationships between networks, means that performance problems might exist in many wide-area networks (WANs). Our main contribution is to continue the cataloging of network inefficiencies so that practitioners and experimenters are aware of them. But, we also show how simple routing detours, can improve throughput by factors of over 3x for client-to-cloud-storage. Although the specific inefficiencies in this paper might be transitory (and we agree with that characterization), WAN bottlenecks due to routing, suboptimal middlebox configuration, and congestion persist as real problems to be cataloged, discussed, and addressed through the use of detours, or data transfer nodes (DTNs), or RONs.

关键词： Cloud-storage Overlay networks Performance evaluation Routing detour

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Enhancing scalability and load balancing of parallel Selected Inversion via tree-based asynchronous communication 30

Enhancing scalability and load balancing of Parallel Selecte...

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Jacquelin, Mathias Yang, Chao Lin, Lin Wichmann, Nathan Lawrence Berkeley Natl Lab Scalable Solvers Grp Berkeley CA 94720 USA Univ Calif Berkeley Dept Math Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Cray Inc Seattle WA USA

ISBN: (纸本)9781509021406

We develop a method for improving the parallel scalability of computations that involve asynchronous task execution. We apply this method to the recently developed parallel selected inversion algorithm [Jacquelin, Lin and Yang 2014], named PSelInv, on massively parallel distributed memory machines. In the PSelInv method, we compute selected elements of the inverse of a sparse matrix A that can be decomposed as A = LU, where L is lower triangular and U is upper triangular. Computing these selected elements of A(-1) requires restricted collective communications among a subset of processors within each column or row communication group created by a block cyclic distribution of L and U. We describe how this type of restricted collective communication can be implemented using asynchronous point-to-point MPI communications combined with a binary tree based data propagation scheme. Because multiple restricted collective communications may take place at the same time, we need to use a heuristic to prevent processors participating in multiple collective communications from receiving too many messages. this heuristic allows us to reduce communication load imbalance and improve the overall scalability of the selected inversion algorithm. For instance, when 6, 400 processors are used, we observe that the use of this heuristic leads to over 5x speedup for a number of test matrices. It also mitigates the performance variability introduced by an inhomogeneous network topology.

关键词： selected inversion distributed memory parallel algorithm asynchronous data communication collective communication high performance computation load balancing

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the Integration of GPU-based and Heterogeneous Devices using HLA 6

The Integration of GPU-based and Heterogeneous Devices using...

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6th Brazilian symposium on Computing Systems Engineering (SBESC)

作者： Andrade, Halamo G. R. Morais, Daniel Silva, thiago W. B. Nascimento, Tiago P. Brito, Alisson V. Univ Fed Paraiba UFPB Joao Pessoa Paraiba Brazil

ISBN: (纸本)9781509026531

the use of distributed components may offer many advantages in the most types of applications. It includes, for example, the easy use of disperse resources in a network, allowing a potential gain on the processing power and data loading. But, the major challenge is interoperability and communication management. In this aspect, the High Level Architecture (HLA) establishes specific policies for data exchanging and time management of communication in the integration of the simulation components. thus, this paper aims to explain and analyse the feasibility to integrate devices based on heterogeneous architectures using distributed and parallel computing, multi-core CPU and GPU, with OpenCL technology. For that, the use of the ieee 1516 standard, called High Level Architecture, is proposed targeting this integration and allowing the use of all computing power from available devices in a distributed system. In this study experiments also were done to demonstrate the approach of running a simple parallel image processing application under the conceived architecture.

关键词： Heterogeneous computing GPU distributed computing

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parallel Peak Pruning for Scalable SMP Contour Tree Computation 6

Parallel Peak Pruning for Scalable SMP Contour Tree Computat...

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6th ieee symposium on Large Data Analysis and Visualization (LDAV)

作者： Carr, Hamish A. Weber, Gunther H. Sewell, Christopher M. Ahrens, James P. Univ Leeds Leeds W Yorkshire England Univ Calif Davis Lawrence Berkeley Natl Lab Davis CA 95616 USA Los Alamos Natl Lab Los Alamos NM 87544 USA

ISBN: (纸本)9781509056590

As data sets grow to exascale, automated data analysis and visualisation are increasingly important, to intermediate human understanding and to reduce demands on disk storage via in situ analysis. Trends in architecture of high performance computing systems necessitate analysis algorithms to make effective use of combinations of massively multicore and distributed systems. One of the principal analytic tools is the contour tree, which analyses relationships between contours to identify features of more than local importance. Unfortunately, the predominant algorithms for computing the contour tree are explicitly serial, and founded on serial metaphors, which has limited the scalability of this form of analysis. While there is some work on distributed contour tree computation, and separately on hybrid GPU-CPU computation, there is no efficient algorithm with strong formal guarantees on performance allied with fast practical performance. We report the first shared SMP algorithm for fully parallel contour tree computation, with formal guarantees of O(lgnlgt) parallel steps and O(nlgn) work, and implementations with up to 10x parallel speed up in OpenMP and up to 50x speed up in NVIDIA thrust.

关键词： topological analysis contour tree merge tree data parallel algorithms

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Topology-Aware GPU Selection on Multi-GPU Nodes 30

Topology-Aware GPU Selection on Multi-GPU Nodes

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30th ieee International parallel and distributed processing symposium (IPDPS)

作者： Faraji, Iman Mirsadeghi, Seyed H. Afsahi, Ahmad Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781509036820

GPU accelerators have successfully established themselves in modern HPC clusters due to their high performance and energy efficiency. To increase the GPU computational power in a cluster node and tackle larger problems, multi-GPU nodes have become the platform of choice for scientific applications. In a multi-GPU node, GPU devices are interconnected together via different communication channels. thus, intranode inter-process communications among GPUs may traverse different paths with different latency and bandwidth capacity. As the number of GPUs within a multi-GPU node increases, the topology of GPU interconnects becomes more hierarchical, effectively increasing the heterogeneity of the GPU communication channels. In this paper, we provide evidence that the performance of different intranode GPU communication channels can be considerably different from each other. this is specially true for larger message sizes. Taking this into account, our goal in this work is to efficiently assign the available GPU devices on a multi-GPU node to MPI processes in order to improve the GPU-to-GPU communication performance. We tackle this challenge by proposing a topology-aware GPU selection scheme. Our scheme is capable of efficiently mapping MPI processes to the available intranode GPU devices, in a way that more intensive inter-process GPU communications take place on the more efficient communication channels. Our experimental results show that our topology-aware GPU selection scheme can improve the communication performance of the microbench-marks with different communication patterns, specifically those with weighted and asymmetrical communications.

关键词： Multi-GPU node MPI Topology-aware GPU Selection Mapping

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