The proceedings contain 28 papers. The topics discussed include: an image comparison circuit design;hardware signal processing unit for one-dimensional variable-length discrete wavelet transform;rapid prototyping of a...
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ISBN:
(纸本)0769524567
The proceedings contain 28 papers. The topics discussed include: an image comparison circuit design;hardware signal processing unit for one-dimensional variable-length discrete wavelet transform;rapid prototyping of a self-timed ALU with fpgas;on the design of two-level reconfigurable architectures;platform for intrinsic evolution of analogue neural networks;design space exploration of coarse-grain reconfigurable DSPs;an FPGA parallel sorting architecture for the burrows wheeler transform;dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices;FPGA implementation of DSVPWM modulator;on the design of an FPGA-based OFDM modulator for IEEE 802.16-2004;VHDL core for 1024-point radix-4 FFT computation;FPGA implementation of an efficient multiplier over finite fields GF(2m);and hardware/software implementation of a discrete cosine transform algorithm using systemC.
Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume that carr...
Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume that carry a code at the bottom of the first page, provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center. The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They reflect the authors' opinions and, in the interests of timely dissemination, are published as presented and without change. Their inclusion in this publication does not necessarily constitute endorsement by the editors or the Institute of Electrical and Electronics Engineers, Inc.
This paper details the design and implementation of three uniform random number generators for use in massively parallel simulations in fpgas. The three different generators are tailored to make use of three different...
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When variables are assigned to registers or memories in fpgas, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional unit...
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ISBN:
(纸本)0769524567
When variables are assigned to registers or memories in fpgas, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional units are writing to the same storage unit. Since in fpgas the area covered by multiplexers is significantly large compared with the area of the overall design, reducing the area of the multiplexers can reduce the overall area occupied by a design. Reducing the area of a design is essential to efficiently utilize the logic area of the fpgas. This paper proposes a solution that applies simulated annealing after binding variables to storage elements. This solution optimizes the assignment of variables onto registers when standard techniques such as clique partitioning are used;and onto on-chip memory banks when two different memory binding techniques are used The savings obtained in terms of multiplexer area reaches 27% with an average of 16%: moreover, the overall logic area savings reaches 17% with an average of 7%.
In this paper, an FPGA arithmetic logic unit architecture for computing elliptic curve scalar multiplication over the binary extension field GF(2 163) is presented. The proposed architecture implements a parallel vers...
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Success has been demonstrated previously in the use of Genetic Algorithms (GAs) for autonomous faulthandling in Field Programmable Gate Array (FPGA) devices, yet the completeness of a given repair can be improved. Thi...
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