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检索条件"任意字段=ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs"

共 71 条记录，以下是41-50 订阅

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An operating system framework for reconfigurable systems

An operating system framework for reconfigurable systems

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5th international conference on Computer and Information Technology

作者： Zhou, B Qiu, WD Peng, CL Fudan Univ Dept Comp & Informat Technol Shanghai 200433 Peoples R China

ISBN: (纸本)076952432X

reconfigurable computing have been accepted as vehicles for both achieving potentially much higher performance than software and maintaining a higher level of flexibility than hardware. However, there is still no much operating system support for it. Based on the essential differences between software-tasks and hardware-tasks, this pa-per presents and implements a RTOS for reconfigurable systems using uniform multitask model, called SHUM-UCOS (Software-Tasks Hardware-Tasks Uniform Management UCOS), which is designed with the UCOSII as prototype. This RTOS traces and manages the usage of re-configurable resources (fpgas), and can improve the utilization Of these resource and the parallelism of the tasks with the hardware-tasks preconfiguration. And it has been proved by experiments that SHUM-UCOS can shorten the migration time from software implements to hardware implements with the performance improvement.

关键词： Computer operating systems

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High-throughput reconfigurable computing: Design and implementation of an idea encryption cryptosystem on the SRC-6e reconfigurable computer

High-throughput reconfigurable computing: Design and impleme...

引用

2005 international conference on Field Programmable Logic and Applications, FPL

作者： Michalski, Allen Buell, Duncan Gaj, Kris CSE Department University of South Carolina 301 Main Street Columbia SC 29208 United States ECE Department George Mason University 4400 University Drive Fairfax VA 22030 United States

ISBN: (纸本)0780393627

The combination of traditional microprocessors workstations and hardware-reconfigurable Field Programmable Gate Arrays (fpgas) has developed a new class of workstations known as reconfigurable computers, with several examples demonstrating significant speedups compared to standalone PC workstations alone. Several platforms implement PC-FPGA communication using common PC peripheral interface buses such as PCI-X. A new approach from SRC Computers implements a high-speed communication interface that increases the throughput compared to PCI interfaces. This paper demonstrates an efficient high-throughput implementation of IDEA encryption using the SRC platform. SRC design choices that influence both throughput and area are evaluated. Detailed analyses of FPGA resource utilizations, data transfer and reconfiguration overheads for the SRC system are provided, and a comparison between SRC and a public domain software implementation of IDEA are given. © 2005 IEEE.

关键词： Computer architecture

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Design space exploration of coarse-grain reconfigurable DSPs

Design space exploration of coarse-grain reconfigurable DSPs

引用

international conference on reconfigurable computing and fpgas (reconfig)

作者： M. Zabel S. Kohler M. Zimmerling T.B. Preuber R.G. Spallek Institute of Computer Engineering Dresden University of Technology Dresden Germany

This work introduces a new digital signal processor (DSP) architecture concept, which provides increased instruction-level parallelism (ILP), flexibility and scalability compared to state-of-the-art DSPs. The concept can be characterized by an enhanced RISC microprocessor with a tightly coupled reconfigurable ALU array, a vector load/store unit and a control flow manipulation unit. These units implement coarse-grain reconfigurable structures by means of switchable contexts. In contrast to previous work, context activation is performed event-driven according to the instruction pointer of the RISC microprocessor. The synchronous operation of the context-controlled functional units enables an ILP comparable to complex VLIW/SIMD processors, without introducing additional instruction overhead. The reconfigurable units can be adapted to the application demands exploiting parallelism more coarse-grain than common instruction-level functional units. To evaluate the concept, we present a parametrizable template model of the DSP architecture based on a standard ARM7 RISC microprocessor. The DSP model includes an architecture description based on our own ADL/simulation environment and a VHDL RTL model for the purpose of FPGA prototype evaluation. Further, we show detailed quantitative performance and utilization evaluation results related to the ALU array geometry, memory transfer bandwidth and the number of configuration contexts. First experiments executing DSP algorithms have indicated that the proposed architecture can exploit more of the potential application parallelism at a reasonable amount of hardware costs compared to conventional digital signal processors

关键词： Space exploration Digital signal processing Reduced instruction set computing Microprocessors Digital signal processors Scalability VLIW Field programmable gate arrays Virtual prototyping Geometry

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Compilation and management of phase-optimized reconfigurable systems

Compilation and management of phase-optimized reconfigurable...

引用

2005 international conference on Field Programmable Logic and Applications, FPL

作者： Styles, Henry W., Luk Department of Computing Imperial College 180 Queen's Gate London United Kingdom

ISBN: (纸本)0780393627

A program phase is an interval over which the working set of the program remains more or less constant. This paper presents a dynamic optimization scheme which uses program phase information to optimize designs for reconfigurable computing. We present a mathematical formulation of the optimization problem and propose a solution which comprises of : (1) A hardware compilation scheme for generating configurations that are specialized for different phases of execution. (2) A runtime system which manages interchange of these configurations to maintain specialization between phase transitions. We report experimental results for Xilinx Virtex fpgas involving OpenGL SPECview-perf benchmarks and demonstrate 95.39% speedup over an optimized uniform rate static design and 11.13% speedup over an optimized multi-initiation interval static design. We present a framework for a posteriori performance analysis and architectural exploration with which we (a) establish a performance upper bound under perfect phase optimization, (b) investigate sensitivity to reconfiguration time, (c) examine the quality of the proposed algorithm for phase-detection. The optimization is shown to be surprisingly insensitive to increased reconfiguration time. Faster reconfiguration yields limited benefits and performance improvements are possible upto 1 second reconfiguration time. © 2005 IEEE.

关键词： Computer architecture

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To accelerate multiple sequence alignment using fpgas

To accelerate multiple sequence alignment using FPGAs

引用

8th international conference on High-Performance computing in Asia-Pacific Region

作者： Xu Lin Zhang Peiheng Bu Dongbo Feng Shengzhong Sun Ninghui Chinese Acad Sci Inst Comp Technol Natl Res Ctr Intellegent Comp Syst Beijing 100080 Peoples R China

ISBN: (纸本)0769524869

Multiple sequence alignment is a fundamental and challenging problem in computational molecular biology. ClustalW, the most widely used multiple sequence alignment software, performs very slowly on hundreds of sequence. Here, we analyze the algorithm complexity of ClustalW as well as the time profile in practice, and then propose a strategy which uses the reconfigurable hardware FPGA to accelerate ClustalW. Comparison with other coarse-grained parallel strategies demonstrates a fine speedup of this strategy and savage of computing resource.

关键词： Field programmable gate arrays (FPGA)

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FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks

FPGA Implementation and Performance Evaluation of AES-CCM Co...

引用

international conference on reconfigurable computing and fpgas (reconfig)

作者： Ignacio Algredo-Badillo Claudia Feregrino-Uribe René Cumplido Miguel Morales-Sandoval Department of Computer Science INAOE Puebla Mexico

reconfigurable architectures are important elements on the design of software radios. Nowadays, diverse platforms are being developed to support multiple tasks; these platforms are designed specially for the different layers of the OSI (Open System Interconnection) reference model. Specifically, the security architectures described in the MAC sublayer should be evaluated, which are based on cryptographic algorithms that require high computational costs. In this work, two proposed AES-CCM hardware architectures for the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards are implemented in diverse FPGA devices to examine implementation costs and performance evaluation. The results presented in this work will be used for designing and developing a reconfigurable platform with software-radio applications, which will include the high-performance AES-CCM hardware architectures meeting the specifications of the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards.

关键词： Field programmable gate arrays Wireless networks Open systems Computer architecture Hardware reconfigurable architectures Software design Software radio Cryptography Computational efficiency

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Design tradeoffs for BLAS operations on reconfigurable hardware

Design tradeoffs for BLAS operations on reconfigurable hardw...

引用

2005 international conference on Parallel Processing

作者： Zhuo, Ling Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los Angeles CA 90089-2562 United States

ISBN: (纸本)0769523803

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated and some basic operations have been implemented as software libraries. With the rapid advances in technology, hardware acceleration of linear algebra applications using fpgas (Field Programmable Gate Arrays) has become feasible. In this paper, we propose FPGA-based designs for several BLAS operations, including vector product, matrix-vector multiply, and matrix multiply. By identifying the design parameters for each BLAS operation, we analyze the design tradeoffs. In the implementations of the designs, the values of the design parameters are determined according to the hardware constraints, such as the available area, the size of on-chip memory, the external memory bandwidth and the number of I/O pins. The proposed designs are implemented on a Xilinx Virtex-II Pro FPGA. © 2005 IEEE.

关键词： Computer hardware

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SHUM-uCOS: A RTOS using multi-task model to reduce migration cost between SW/HW tasks

SHUM-uCOS: A RTOS using multi-task model to reduce migration...

引用

9th international conference on Computer Supported Cooperative Work in Design

作者： Zhou, B Qiu, WD Chen, Y Peng, CL Fudan Univ Dept Comp & Informat Technol Shanghai 200433 Peoples R China

ISBN: (纸本)1846000025

The design of embedded systems has become more complex than ever, and the design qualities depend more on the cooperation of multidisciplinary design teams: hardware engineers and software engineers in general. However, due to the lack of uniform programming model and system components for these different teams, the migrations costs of a function model from software to hardware are high. But these actions are necessary in the hardware-software partitioning of embedded systems, especially in the prototype designs. To cope with this problem, we adopt a uniform multi-task model and implement a RTOS (Real-Time Operating System), called SHUM-uCOS, which deals with hardware functions as same as software tasks. This RTOS uses uCOSII as its prototype, traces and manages the states of reconfigurable resources (fpgas), which allows the execution of hardware tasks in a true multitasking manner. Moreover, SHUM-uCOS also defines a standard hardware-task interface, which supports share-bus protocol. It has been proved by experiments that SHUM-uCOS can shorten the migration time from software implementations to hardware implementations with the performance improvement.

关键词： reconfigurable computing system RTOS multi-task model uCOS

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PGR: A software package for reconfigurable super-computing

PGR: A software package for reconfigurable super-computing

引用

2005 international conference on Field Programmable Logic and Applications, FPL

作者： Hamada, Tsuyoshi Nakasato, Naohito 2-1 Hirosawa Wako Saitama 351-0198 Japan RIKEN

ISBN: (纸本)0780393627

In this paper, we describe a methodology for implementing FPGA-based accelerator(FBA) from a high-level specification language. We have constructed a software package specially tuned for accelerating particle-based scientific computations with an FBA. Our software generates (a)a suitable configuration for the FPGA, (b) the C source code for interfacing with the FBA, and (c) a software emulator. The FPGA configuration is build by combining components from a library of parametrized arithmetic modules;these modules implement fixed-point, floating-point and logarithmic number system with flexible bitwidth and pipeline stages. To make certain our methodology is effective, we have applied our methodology to acceleration of astrophysical N-body application with two types of platforms. One is our PROGRAPE-3 with four XC2VP70-5 fpgas and another is a minimum composition of CRAY-XD1 with one XC2VP50-7 FPGA. As the result, we have achieved peak performance of 324 Gflops with PROGRAPE-3 and 45 Gflops with the minimum CRAY-XD1, sustained performance of 236 Gflops with PROGRAPE-3 and 34 Gflops with the CRAY-XD1. © 2005 IEEE.

关键词： Supercomputers

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A system-level design methodology for reconfigurable computing applications

A system-level design methodology for reconfigurable computi...

引用

IEEE international conference on Field-Programmable Technology (FPT)

作者： E. El-Araby T. El-Ghazawi K. Gaj George Washington University USA George Mason University USA

reconfigurable computers (RCs) can leverage the synergism between conventional processors and fpgas by combining the flexibility of traditional microprocessors with the parallelism of hardware and reconfigurability of fpgas. However, there exist multiple challenges that must be resolved to be able to develop efficient applications for reconfigurable computing systems. One of these challenges is the lack of formal modeling/design methodology. This work, addresses the need for a formal design methodology. In particular, a structured design life-cycle, which can be applied at the reconfigurable computing systems rather than at the chip-level as it has been traditionally the case, is conceptually proposed, formally modeled and experimentally verified.

关键词： System-level design Computer applications Computer architecture Application software Design methodology Concurrent computing Field programmable gate arrays Parallel processing Space exploration Throughput

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