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检索条件"任意字段=ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs"

共 71 条记录，以下是51-60 订阅

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A reconfigurable architecture for implementing multiple cipher algorithms

A reconfigurable architecture for implementing multiple ciph...

引用

IEEE international conference on Field-Programmable Technology (FPT)

作者： A. Valizadeh M. Saheb Zamani B. Sadeghian F. Mehdipour Shahriar-Shahre Ghods Branch Islamic Azad University Tehran Iran Amirkabir University of Technology슠 Tehran Iran

reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. In this paper, we implemented multiple cryptographic algorithms, namely DES, LOKI, DESX, Biham-DES, and S/sup n/DES on a reconfigurable hardware. Our implementation results in a high flexibility and similar ciphering rate in compare with the previous implementations reported in fpgas.

关键词： reconfigurable architectures Cryptography Hardware Software algorithms Field programmable gate arrays Data communication Communication switching Data security Cryptographic protocols Scheduling algorithm

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An Efficient Fpga Based Sequential Implementation of Advanced Encryption Standard

An Efficient Fpga Based Sequential Implementation of Advance...

引用

ITI international conference on Information and Communications Technology (ICICT)

作者： A. Aziz N. Ikram National University of Science and Technology Karachi Pakistan GPO National University of Science and Technology Islamabad Pakistan

This paper describes an efficient sequential implementation of advanced encryption standard (AES) algorithm on a field programmable gate arrays (fpgas) especially targeting it for feedback modes. The design of S-box in the RAM blocks of the devices has resulted in enhanced throughput as well as real estate savings on the development platform. The use of FPGA in cryptographic system has many advantages. reconfigurable implementation benefit from the hardware based performance of custom VLSI, while maintaining the flexibility of software. With the ever increasing computational power vis-a-vis decreasing costs, reconfigurable devices like fpgas have become attractive for embedding cryptographic. The throughput of 2.966 Gbps has been achieved with limiting the required area to 481 slices

关键词： Field programmable gate arrays Cryptography Throughput Feedback Hardware Very large scale integration Software maintenance Software performance Embedded computing Costs

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Towards a reconfigurable tracking system

Towards a reconfigurable tracking system

引用

international conference on Field Programmable Logic and Applications

作者： Sebastien C. Wong Mark Jasiunas David Kearney Electronic Warfare & Radar Division Defence Science and Technology Organisation Edinburgh SA Australia Advanced Computing Research Centre University of South Australia Mawson Lakes SA Australia

Robust real-time automatic detection tracking and classification of objects in imagery is one of the most computationally demanding tasks in computer vision. Historically the field of computer vision has been limited by computing power. In particular algorithms that require multiple correlations, convolutions and other complex operations can be prohibitive to implement on a microprocessor. Part of the poor performance of microprocessors is their serial nature, while many of these operations are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASIC). Another approach is to use Field Programmable Gate Arrays (fpgas) and reconfigurable computing. reconfigurable computing offers a trade-off between the speed of hardware and flexibility of software. This paper describes two computationally intensive tracking algorithms, investigates their implementation on a reconfigurable computer, and benchmarks their performance. From our preliminary results we find that reconfigurable computing is well suited to the implementation of real-time tracking systems.

关键词： Computer vision Australia Object detection Layout Field programmable gate arrays Radar tracking Lakes Microprocessors Hardware Image recognition

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A run-time reconfigurable hardware infrastructure for IP-core evaluation and test

A run-time reconfigurable hardware infrastructure for IP-cor...

引用

international conference on Field Programmable Logic and Applications

作者： R. Siripokarpirom Department of Distributed Systems Technical University Hamburg-Harburg Germany

In recent years, there has been increasing interest in exploiting the partial and run-time reconfiguration of fpgas to develop novel computing systems and applications. This paper proposes a generic, reusable FPGA-based test platform that relies on the run-time reconfigurability of the Xilinx Virtex family of fpgas and allows a number of hardware components such as Intellectual Property (IP) cores to be loaded into the hardware during run-time for testing and evaluation purposes. The platform can be incorporated into a software-based simulation environment, thus allowing software models or testbenches to interact with the hardware modules inside the FPGA in a co-simulation/emulation manner. A case study is also given to demonstrate the practicality and correctness of a proof-of-concept implementation of the proposed platform.

关键词： Runtime Hardware Field programmable gate arrays Circuit testing Software testing System testing Computer applications Distributed computing Intellectual property Emulation

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On-line synthesis for partially reconfigurable fpgas

On-line synthesis for partially reconfigurable FPGAs

引用

international conference on VLSI Design

作者： Renqiu Huang R. Vemuri University of Cincinnati Cincinnati OH USA

ISBN: (纸本)0769522645

An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-line routing are the three essential steps in implementing an incoming task on the FPGA during run-time. Whereas there has been some research in on-line placement, on-line synthesis received relatively little attention. We present what is believed to be the first on-line synthesis methodology for partially reconfigurable fpgas. In on-line synthesis, time for synthesis should be kept low while ensuring the placeability of the synthesized design on the FPGA in the available empty area and meeting the performance requirements. We ensure placeability by considering and maintaining the available area on the FPGA surface as a collection of maximal empty rectangles. The proposed synthesizer allocates the FPGA resources adoptively and is incremental in nature. The algorithm is designed to be linear in terms of the number of operations to ensure its on-line usage. Our experimental results demonstrate the advantages of the proposed approach.

关键词： Field programmable gate arrays High level synthesis Resource management Scheduling Routing Runtime Algorithm design and analysis Synthesizers Mobile computing Operating systems

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High Performance computing using reconfigurable Hardware

High Performance Computing using Reconfigurable Hardware

引用

Mexican international conference on Computer Science (ENC)

作者： V.K. Prasanna Electrical engineering and computer science University of Southern California

Recently, several state of the art high end platforms have incorporated fpgas for application acceleration. This talk explores optimizations for accelerating linear algebra computations on such systems. We develop algorithmic optimizations for such systems and demonstrate the suitability of fpgas for floating point intensive computations. We discuss the design of a BLAS library for such systems and develop a highly optimized reduction circuit for such architectures. Using the reduction circuit, we demonstrate superior performance for sparse matrix computations. The performance of fpgas is also compared against those of state-of-the-art embedded processors, general purpose processors, and DSPs for floating point intensive applications.

关键词： High performance computing Hardware Field programmable gate arrays Acceleration Circuits Linear algebra Libraries Design optimization Computer architecture Sparse matrices

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Prototyping automatic cloud cover assessment (ACCA) algorithm for remote sensing on-board processing on a reconfigurable computer

Prototyping automatic cloud cover assessment (ACCA) algorith...

引用

IEEE international conference on Field-Programmable Technology (FPT)

作者： E. El-Araby M. Taher T. El-Ghazawi J. Le Moigne George Washington University USA NASA''s Goddard Space Flight Center USA

Clouds have a critical role in many studies, e.g. weather- and climate-related studies. However, they represent a source of errors in many applications, and the presence of cloud contamination can hinder the use of satellite data. This requires a cloud detection process to mask out cloudy pixels from further processing. The trend for remote sensing satellite missions has always been towards smaller size, lower cost, more flexibility, and higher computational power. reconfigurable computers (RCs) combine the flexibility of traditional microprocessors with the power of field programmable gate arrays (fpgas). Therefore, RCs are a promising candidate for on-board preprocessing. This paper presents the design and implementation of an RC-based real-time cloud detection system. We investigate the potential of using RCs for on-board preprocessing by prototyping the Landsat 7 ETM+ ACCA algorithm on one of the state-of-the art reconfigurable platforms, SRC-6E. Although a reasonable amount of investigations of the ACCA cloud detection algorithm using fpgas has been reported in the literature, very few details/results were provided and/or limited contributions were accomplished. Our work has been proven to provide higher performance and higher detection accuracy

关键词： Prototypes Remote sensing Cloud computing Satellites Field programmable gate arrays Computer errors Application software Contamination Costs Microprocessors

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High-throughput reconfigurable computing: design and implementation of an IDEA encryption cryptosystem on the SRC-6E reconfigurable computer

High-throughput reconfigurable computing: design and impleme...

引用

international conference on Field Programmable Logic and Applications

作者： A. Michalski D. Buell K. Gaj CSE Department University of South Carolina Columbia SC USA ECE Department George Mason University Fairfax VA USA

The combination of traditional microprocessors workstations and hardware-reconfigurable field programmable gate arrays (fpgas) has developed a new class of workstations known as reconfigurable computers, with several examples demonstrating significant speedups compared to standalone PC workstations alone. Several platforms implement PC-FPGA communication using common PC peripheral interface buses such as PCI-X. A new approach from SRC Computers implements a highspeed communication interface that increases the throughput compared to PCI interfaces. This paper demonstrates an efficient high-throughput implementation of IDEA encryption using the SRC platform. SRC design choices that influence both throughput and area are evaluated. Detailed analyses of FPGA resource utilizations, data transfer and reconfiguration overheads for the SRC system are provided, and a comparison between SRC and a public domain software implementation of IDEA are given.

关键词： Cryptography Field programmable gate arrays Microprocessors Workstations Throughput Bandwidth Coprocessors Random access memory Computer interfaces Open source software

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A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware

A heuristic approach to schedule periodic real-time tasks on...

引用

international conference on Field Programmable Logic and Applications

作者： K. Danne M. Platzner Department of Computer Science University of Paderborn Germany

This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as fpgas. reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations.

关键词： Hardware Field programmable gate arrays Computer science Time factors Testing Telecommunication computing Logic programming Processor scheduling Control systems Telecommunication control

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Compilation and management of phase-optimized reconfigurable systems

Compilation and management of phase-optimized reconfigurable...

引用

international conference on Field Programmable Logic and Applications

作者： H. Styles W. Luk Department of Computing Imperial College London London UK

A program phase is an interval over which the working set of the program remains more or less constant. This paper presents a dynamic optimization scheme which uses program phase information to optimize designs for reconfigurable computing. We present a mathematical formulation of the optimization problem and propose a solution which comprises of: (1) a hardware compilation scheme for generating configurations that are specialized for different phases of execution. (2) A runtime system which manages interchange of these configurations to maintain specialization between phase transitions. We report experimental results for Xilinx Virtex fpgas involving OpenGL SFHCview-perf benchmarks and demonstrate 95.39% speedup over an optimized uniform rate static design and 11.13% speedup over an optimized multiinitiation interval static design. We present a framework for a posteriori performance analysis and architectural exploration with which we (a) establish a performance upper bound under perfect phase optimization, (b) investigate sensitivity to reconfiguration time, and (c) examine the quality of the proposed algorithm for phase-detection. The optimization is shown to be surprisingly insensitive to increased reconfiguration time. Faster reconfiguration yields limited benefits and performance improvements are possible up to 1 second reconfiguration time.

关键词： Design optimization Runtime Field programmable gate arrays Microprocessors Costs Educational institutions Performance analysis Phase detection Roads Predictive models

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