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30th International Conference on Parallel and Distributed Processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied computing, CSCE 2024

作者： Yaguchi, Kazuki Maeda, Eriko Kawai, Shunya Teruya, Daichi Osana, Yasunori Miyoshi, Takefumi Nakajo, Hironori Department of Electrical Engineering and Computer Science Graduate School of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan Research and Education Institute for Semiconductors and Informatics Kumamoto University 2-39-1 Kurokami Kumamoto Chuo-ku860-8555 Japan WasaLabo LLC. K-2 Buransyu 6-5-20 Minaminaruse Tokyo Machida-shi194-0045 Japan Division of Advanced Information Technology and Computer Science Institute of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan

ISBN: (纸本)9783031856372

In recent years, hardware acceleration in large-scale computing fields such as Artificial Intelligence and High Performance computing, faces hardware resource shortages. To overcome this problem, we propose reconfigurable Virtual Accelerator (ReVA), which allows a large-scale acceleration circuit built using multiple fpgas, processors and memory subsystems, to accelerate application programs. We have designed and implemented a prototype of Virtual Accelerator (VA) Generator for ReVA to investigate its performance. The VA Generator prototype employs an open-source HLS automated split compilation tool, RapidStream, to automatically generate placed-and-routed virtual accelerators that can be implemented on multiple fpgas based on HLS dataflow designs. The VA Generator, which places VAs on the appropriate regions of fpgas, allows large circuits to be performed like a single accelerator using several fpgas. In addition, RapidStream’s parallel compilation technology allows the VA Generator to suppress the increasing compilation time according to the circuit size. Moreover, with our VA Generator prototype we have built and evaluated a VA of a large-scale circuit which cannot be fit in a single FPGA with multiple fpgas. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： reconfigurable hardware

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Building Simulation Environment of reconfigurable Virtual Accelerator (ReVA) 30th

Building Simulation Environment of Reconfigurable Virtual A...

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作者： Kawai, Shunya Maeda, Eriko Yaguchi, Kazuki Osana, Yasunori Miyoshi, Takefumi Nakajo, Hironori Tokyo University of Agriculture and Technology Graduate School of Engineering Tokyo Japan Kumamoto University Research and Education Institute for Semiconductors and Informatics Kumamoto Japan WasaLabo LLC. Tokyo Japan Tokyo University of Agriculture and Technology Institute of Engineering Tokyo Japan

ISBN: (纸本)9783031856372

In recent years, research in AI and HPC has explored accelerating computations using fpgas. High-Level Synthesis (HLS) is beneficial for implementing algorithms from these fields onto fpgas as circuits. However, since the circuits generated by HLS are generally larger than those designed with HDL. Moreover, the operations in these fields tend to increase in number and complexity, and the FPGA resources required are increasing accordingly. Therefore, using fpgas in practice presents challenges regarding resource restrictions. To address these issues, we are researching reconfigurable Virtual Accelerator (ReVA), which allows the sharing of resources across multiple fpgas and enables the implementation of large-scale circuits. ReVA creates and shares virtual accelerators (VAs) using the resources of multiple fpgas. processors and VAs in a ReVA share data using distributed shared memory (DSM). Furthermore, the data on the VA and DSM are dynamically arranged so that access from each of the processors used is the shortest. In this paper, we propose and implement ReVA Simulator. ReVA Simulator can reproduce ReVA operation without the need to prepare an actual device with an FPGA, processor and memory connected. Furthermore, we estimated the execution time when utilizing ReVA and conducted evaluations. The evaluation result shows that ReVA simulator achieves FFT reduced by 36% against execution in C. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： High level synthesis

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Femtosecond-laser written universal quantum photonic processors 3

Femtosecond-laser written universal quantum photonic process...

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Quantum computing, Communication, and Simulation III 2023

作者： Pentangelo, C. Ceccarelli, F. Di Giano, N. Arpe, R. Piacentini, S. Crespi, A. Osellame, R. Dipartimento di Fisica Politecnico di Milano piazza Leonardo da Vinci 32 Milano20133 Italy piazza Leonardo da Vinci 32 Milano20133 Italy

ISBN: (纸本)9781510659971

Photonic integrated circuits (PICs) are a technology with a growing interest in a wide range of applications in quantum information, from computation to communications and sensing. Amongst the various types of PICs, universal quantum photonic processors (UQPPs) are programmable photonic integrated circuits on which any arbitrary unitary transformation can be implemented on a given input quantum photonic state, sometimes also referred to as quantum photonic fpgas. Various kinds of UQPPs have been reported, mostly with a reconfigurable Mach-Zehnder interferometer (MZI) as building block, in photonic platforms ranging from silicon nitride to glass-based direct laser writing. Among them, femtosecond laser writing (FLW) is a versatile fabrication technique that allows for cost-effective fabrication of waveguides in glass substrates with low insertion losses (down to 0.1 dB cm−1 for the propagation and 0.2 dB per facet for the coupling) over a wide wavelength range, a key requirement for quantum applications. Moreover, FLW allows for the fabrication of microstructures in the substrate such as trenches, which can act as thermal isolation structures that significantly reduce the power dissipation of thermal phase shifters and their thermal crosstalk. In this work, firstly we present the fabrication of a 6-mode FLW-UQPP in a rectangular MZI mesh layout operating at 785 nm with average amplitude fidelity as high as 0.9963 when implementing switching unitaries and 0.9979 when implementing Haar random unitaries. Secondly, we demonstrate the versatility of the FLW platform by fabricating another 6-mode UQPP with waveguides optimized for operation at 1550 nm wavelength, with similar performance, on which we repeated the implementation of Haar random unitaries with 0.9969 average amplitude fidelity. © 2023 SPIE.

关键词： Fabrication

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Customizable Heterogeneous Acceleration for Tomorrow's High-Performance computing 17

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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2015 IEEE 17th International Conference on High Performance computing and communications (HPCC)

作者： Cilardo, Alessandro Flich, Jose Gagliardi, Mirko Gavila, Rafael T. Univ Naples Federico II DIETI Naples Italy Univ Politecn Valencia GAP Valencia Spain

ISBN: (纸本)9781479989379

High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to fpgas, might play for tomorrow's high-performance computing.

关键词： field programmable gate arrays graphics processing units multiprocessing systems network-on-chip parallel processing power aware computing quality of service FPGA GPU-like processors NoC-based many-core system QoS-sensitive computing customizable heterogeneous acceleration heterogeneous acceleration heterogeneous manycore systems high-level design principles high-performance computing innovative architecture medium-end CPU multicore processors power-efficient high-performance computing reconfigurable hardware regions Acceleration Computer architecture Field programmable gate arrays Hardware Program processors Quality of service Registers Field programmable gate arrays High Performance computing Quality of service power aware computing Program processors Multiprocessing systems network-on-chip Computer Architecture Registers acceleration PARALLEL PROCESSING (COMPUTERS) Multi-core processors Computer hardware Graphics Processing Unit

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Side channel attack on multiprecision multiplier used in protected ECDSA implementation

Side channel attack on multiprecision multiplier used in pro...

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International Conference on reconfigurable computing and fpgas, ReConFig 2015

作者： Varchola, Michal Drutarovsky, Milos Repka, Marek Zajac, Pavol Department of Electronics and Multimedia Communications Technical University of Kosice Kosice Slovakia Department of Computer Science and Mathematics Slovak University of Technology in Bratislava Bratislava Slovakia

ISBN: (纸本)9781467394062

When considering Elliptic Curve Cryptography (ECC) implementations, countermeasures against side channel attacks are primarily focused on elliptic curve arithmetic. On the other hand, Elliptic Curve Digital Signature Algorithm (ECDSA) implementation also uses a modular multiplication of a private key dA, and publicly known random parameter r. The side channel leakage of the multiplication rdA can reveal the private key, especially in systems with narrow-width data-path used for multiprecision arithmetic. The proposed countermeasure is based on the different order of arithmetic operations, masking the critical multiplication by a random ephemeral key k-1. In this work, we demonstrate a special variant of collision attack against the protected ECDSA signature computation. The collision attack exploits the leakage from multiprecision integer multiplier, which is a building block of several published scalable FPGA-enabled ECC crypto-processors. Our concrete experimental results were obtained from hardware DISIPA platform based on Altera Cyclone III FPGA. © 2015 IEEE.

关键词： Side channel attack

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Side channel attack on multiprecision multiplier used in protected ECDSA implementation

Side channel attack on multiprecision multiplier used in pro...

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International Conference on reconfigurable computing and fpgas (ReConFig)

作者： Michal Varchola Milos Drutarovsky Marek Repka Pavol Zajac Department of Electronics and Multimedia Communications Technical University of Kosice Kosice Slovakia Department of Computer Science and Mathematics Slovak University of Technology in Bratislava Bratislava Slovakia

关键词： Elliptic curve cryptography Field programmable gate arrays Power measurement Power demand Digital signatures Pollution measurement

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Customizable Heterogeneous Acceleration for Tomorrow's High-Performance computing

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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IEEE International Symposium on Cyberspace Safety and Security

作者： Alessandro Cilardo Jose Flich Mirko Gagliardi Rafael T. Gavila DIETI - University of Naples Federico II GAP - Universitat Politecnica de Valencia

ISBN: (纸本)9781479989386

High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based many-core system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to fpgas, might play for tomorrow's high-performance computing.

关键词： High Performance computing PROCESSOR Multi-core processors acceleration

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A Comparison Study on Implementing Optical Flow and Digital communications on fpgas and GPUs

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2010年第2期3卷 1–22页

作者： Bodily, John Nelson, Brent Wei, Zhaoyi Lee, Dah-Jye Chase, Jeff Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing computations. Applications successfully implemented on fpgas typically contain high levels of parallelism and often use simple statically scheduled control and modest arithmetic. Recently introduced computing devices such as coarse-grain reconfigurable arrays, multi-core processors, and graphical processing units promise to significantly change the computational landscape and take advantage of many of the same application characteristics that fit well on fpgas. One real-time computing task, optical flow, is difficult to apply in robotic vision applications because of its high computational and data rate requirements, and so is a good candidate for implementation on fpgas and other custom computing architectures. This article reports on a series of experiments mapping a collection of different algorithms onto both an FPGA and a GPU. For two different optical flow algorithms the GPU had better performance, while for a set of digital comm MIMO computations, they had similar performance. In all cases the FPGA implementations required 10x the development time. Finally, a discussion of the two technology's characteristics is given to show they achieve high performance in different ways.

关键词： Experimentation Design Performance Measurement Digital communications FPGA GPU optical flow reconfigurable computing

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Non-instruction fetch-based architecture reduces almost 100% of the dynamic power and energy

Non-instruction fetch-based architecture reduces almost 100%...

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作者： Renbi, Abdelghani Lindh, Lennart Delsing, Jerker Eislab Luleå University of Technology Sweden Embedded Systems Department Jönköping University Sweden

ISBN: (纸本)9780769543314

This paper demonstrates the benefit of fpgas for better power and energy efficiency when exploited for noninstruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100% of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by improving the IT sector's CO2 emissions. The work involves three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs employ a single-purpose processor with different number of storage registers 2n and 2n2 and the third design uses a computer system piloted by NIOS II/e processor with on-chip memory. The designs were captured in VHDL language and prototyped on an Altera Cyclone II EP2C35F672C6 device. Both synthesis and place&route steps were performed with Quartus II 6.0 Web Edition. The experiments were made on Altera DE2 board. In this paper we have also clarified further the power estimation error of Altera power estimation tools, which we have evaluated in [1]. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Non-Instruction Fetch-Based Architecture Reduces Almost 100 Percent of the Dynamic Power and Energy

Non-Instruction Fetch-Based Architecture Reduces Almost 100 ...

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IEEE/ACM Int'l Conference on & Int'l Conference on Cyber, Physical and Social computing (CPSCom) Green computing and communications (GreenCom)

作者： Abdelghani Renbi Lennart Lindh Jerker Delsing Eislab Luleå University of Technology Sweden Embedded Systems Department Jönköping University Sweden

This paper demonstrates the benefit of fpgas for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by improving the IT sector's CO2 emissions. The work involves three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs employ a single-purpose processor with different number of storage registers 2n and 2n 2 and the third design uses a computer system piloted by NIOS II/e processor with on-chip memory. The designs were captured in VHDL language and prototyped on an Alter a Cyclone II EP2C35F672C6 device. Both synthesis and place&route steps were performed with Quart us II 6.0 Web Edition. The experiments were made on Altera DE2 board. In this paper we have also clarified further the power estimation error of Alter a power estimation tools, which we have evaluated in.

关键词： Computer architecture Field programmable gate arrays Clocks Transmission line matrix methods Estimation error Embedded systems Power demand

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