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International Conference on Education technology and Computer, ICETC

作者： Amrita Saha Amitabha Sinha School of Information Technology West Bengal University of Technology Kolkata India

Major functions of ldquoSoftware Defined Radios( SDRs )rdquo are signal processing functions (SPF) and the basic building blocks for most of these functions are multipliers, adders, delays, square roots, trigonometric functions etc.. The SPFs are computationally intensive and they exhibit spatial or temporal parallelism or both. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently, state-of-the-art fpgas have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions because of the availability of in-built multiply and accumulate (MAC) units within these chips. Hence, fpgas are becoming possible hardware platforms for implementing SDRs. Apart from that these fpgas also include partial reconfiguration features that make them suitable for implementing SDRs efficiently as the configuration latency in run time trends to go down. This paper investigates the potential use of fpgas for implementing efficient ldquoRadio Processorrdquo. The proposed Processor is based on a parallel re-configurable which was implemented on FPGA and exploits the spatial and temporal parallelism of the signal processing functions using a new concept ldquoreconfigurable Single Function Multiple Data (RSFMD)rdquo architecture. The architecture was validated on Xilinx Virtex iv FPGA.

关键词： Software radio Field programmable gate arrays Computer architecture Signal processing Concurrent computing Parallel processing Hardware Added delay Digital signal processing chips System-on-a-chip

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An overview of a compiler for mapping software binaries to hardware

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2007年第11期15卷 1177-1190页

作者： Mittal, Gaurav Zaretsky, David Tang, Xiaoyong Banerjee, Prith Univ Illinois Dept Elect & Comp Engn Chicago IL 60607 USA Binachip Inc Kyoto 60601 Japan Magma Design Automat San Jose CA 95110 USA Univ Illinois Coll Engn Chicago IL 60607 USA

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (fpgas) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C6211 DSP (VLIW) and the ARM 922T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix fpgas. We record overall performance gains of 1.5-26.9 x for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.

关键词： binary translation compiler decompilation hardware-software codesign high-level synthesis reconfigurable computing

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Memory Optimized Architecture for Efficient Gauss-Jordan Matrix Inversion

Memory Optimized Architecture for Efficient Gauss-Jordan Mat...

引用

Southern Conference on Programmable Logic

作者： Goncalo M. de Matos Horacio C. Neto INESC-ID / IST / UTL Technical University of Lisbon Portugal

This paper presents a new architecture for efficient Gauss-Jordan matrix inversion algorithm on reconfigurable hardware platforms. The results show that currently available re- configurable computing technology can easily achieve significantly higher floating-point performance than high-end CPUs, running state-of-the-art routines for large matrices operations. For common reconfigurable systems, where the fpgas are directly coupled to the on-board memory, the achievable performance scales directly with the number of realizable simultaneous memory accesses. A new dedicated reconfigurable architecture is proposed and analysed and the results show a performance improvement of 2x over the previous implementation, using only half of the memory and half of the floating-point units. Benchmarking against Matlab, which features high performance matrix inversion routines, shows that a 100 MHz FPGA can easily surpass the performance of 3,2 GHz Intel Pentium iv processors. This is possible having only 5 double-port memory banks or 9 single-port memory banks connected to the FPGA.

关键词： Memory architecture Gaussian processes Field programmable gate arrays Matrices Circuits Performance analysis Computer architecture Hardware reconfigurable architectures Power engineering computing

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An 8 GHz ultra wideband transceiver prototyping testbed

An 8 GHz ultra wideband transceiver prototyping testbed

引用

International Workshop on Rapid System Prototyping (RSP)

作者： D. Agarwal C.R. Anderson P.M. Athanas Configurable Computing Lab Virginia Polytechnic Institute and State University Blacksburg VA USA Mobile and Portable Radio Research Group Bradley Department of Electrical Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and fpgas. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125 ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s.

关键词： Ultra wideband technology Transceivers Prototypes Testing Field programmable gate arrays Software radio Sampling methods Clocks Signal processing Logic

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Proceedings of SPIE: reconfigurable technology;fpgas and reconfigurable processors for computing and communications iv

Proceedings of SPIE: Reconfigurable technology;FPGAs and rec...

引用

reconfigurable technology: fpgas and reconfigurable processors computing and communications iv

The proceedings contains 12 papers from the conference on Proceedings of SPIE: reconfigurable technology: fpgas and reconfigurable Process for computing and communications iv. Topics discussed include: single-instruction set architectures for image processing;design flow for the reconfigurable HW platform XPP;framework for development and distribution of hardware acceleration;optimizing parallel programs for hardware implementation;defect tolerant fine-grained parallel testing of a cell matrix;parameterizing reconfigurable designs for image warping;and reconfigurable logic design case.

关键词： Internet

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reconfigurable logic design case

Reconfigurable logic design case

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications iv

作者： Ma, F Knight, J Plett, C Carleton Univ Dept Elect Ottawa ON K1S 5B6 Canada

ISBN: (纸本)0819446467

This design case identifies generalizable features of a course-grained reconfigurable FPGA, Chameleon's reconfigurable platform. An FFT is used to identify typical design practices, problems, and solutions in targeting such a platform. This paper focuses on datapath mapping, separating it into functional design and placement of reconfigurable resources. In addition to exploring the design methodology, it analyzes numerical artifacts, demonstrates efficient packing of the data path, and highlights differences from ASIC design.

关键词： reconfigurable platform-based design coarse grain FPGA

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Single instruction set Architectures for image processing

Single instruction set Architectures for image processing

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications iv

作者： Laplante, P Gilreath, W Penn State Great Valley Malvern PA 19355 USA

ISBN: (纸本)0819446467

For more than fifty years, computer engineers have sought to construct minimal computers using only a single instruction computer. While it might appear to be a simple academic exercise, remarkably, a rich computation paradigm can be developed using this approach, with important applications and implications in reconfigurable, chemical, optical and biological computing. More recently, the widespread use of the Field Programmable Gate Array (FPGA) has made such an approach not only desirable, but also practical. In this paper the history and motivation behind single instruction or one instruction computing (OISC) is reviewed. It is then shown how the paradigm can be used to implement a variety of imaging operations efficiently. Finally, a practical application and future work in languages and tools are presented.

关键词： OISC one-instruction computing image processing reconfigurable computing

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Implementing a dynamically reconfigurable ATM switch on the VIRTEX FPGA of the FPX platform

Implementing a dynamically reconfigurable ATM switch on the ...

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications iv

作者： Horta, EL Lockwood, JW Kofuji, ST Univ Sao Paulo Escola Politecn Integrated Syst Lab Dept Elect Engn BR-05508900 Sao Paulo Brazil

ISBN: (纸本)0819446467

This paper shows how a reconfigurable ATM switch (RECATS) has been implemented on a single VIRTEX FPGA. present in the Field Programmable Port Extender board (FPX). The switch architecture is outlined and the FPX platform is described in detail. Finally, the modifications applied to the FPX components and the methodology used to validate the reconfigurable switch are explained.

关键词： reconfigurable logic partial RTR ATM switch dynamic reconfiguration VIRTEX FPGA

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Parameterising reconfigurable designs for image warping

Parameterising reconfigurable designs for image warping

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications iv

作者： Jun, J Schmidt, S Luk, W Rueckert, D Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2BZ England

ISBN: (纸本)0819446467

This paper describes reconfigurable, computing techniques for optimising image warping designs. Our image warping algorithm is based on radial basis functions, which enable the warping effect to be specified in terms of feature points. The coefficients of the warping function are obtained from the Symmetric Bipartite Table Method (SBTM), and the lookup tables can be generated dynamically at run time. We have deployed an optimised number representation involving both custom integer and custom floating-point formats in computing the radial function approximation. Furthermore, a fully-pipelined design has been developed in the Handel-C language, which can perform image warping in real time for resolutions up to 256 by 256 pixels on a Xilinx XC2V6000 device. This design is parameterisable at compile time for different image resolutions. Currently our implementation on a Xilinx Virtex XCV1000 device for the RC1000-PP platform achieves 50% faster than a software version on an AMD Athlon 1.4 GHz PC. A faster data bus and a larger FPGA for the RC1000-PP platform can result in a further speed improvement of over ten times.

关键词： image warping custom computing symmetric bipartite table method reconfigurable design

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Design flow for the reconfigurable HW platform XPP

Design flow for the reconfigurable HW platform XPP

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications iv

作者： Ritter, C Schüler, E Sax, E Müller-Glaser, KD Res Ctr Comp Sci Karlsruhe FZI D-76131 Karlsruhe Germany

ISBN: (纸本)0819446467

Due to an increasing technology progress in the configurable hardware sector, which is currently dominated by fpgas, new approaches like very fast re-configurable devices with ALU level granularity are on the rise. However, these coprocessor devices can not be programmed with conventional HW nor SW design approaches. To solve this dilemma, a combination is needed. This approach is described in this paper. Furthermore, an example how to program a reconfigurable device is illustrated. This example consists of parts of an NTEG-4 decoder, which is running on the reconfigurable processor platform XPP. The partitioning of these decoding algorithms into modules and the means of interaction between these modules is highlighted. In addition, the embedding of this algorithm in a XPP system is outlined.

关键词： run-time reconfiguration dataflow processor XPP MPEG4 decoder

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