This paper describes IGOL, a framework for developing reconfigurable data processing applications. While IGOL was originally designed to target imaging and graphics systems, its structure is sufficiently general to su...
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ISBN:
(纸本)0819446467
This paper describes IGOL, a framework for developing reconfigurable data processing applications. While IGOL was originally designed to target imaging and graphics systems, its structure is sufficiently general to support a broad range of applications. IGOL adopts a four-layer architecture: application layer, operation layer, appliance layer and configuration layer. This architecture is intended to separate and co-ordinate both the development and execution of hardware and software components. Hardware developers can use IGOL as an instance testbed for verification and benchmarking, as well as for distribution. Software application developers can use IGOL to discover hardware accelerated data processors, and to access them in a transparent, non-hardware specific manner. IGOL provides extensive support for the RC1000-PP board via the Handel-C language, and a wide selection of image processing filters have been developed. IGOL also supplies plug-ins to enable such filters to be incorporated in popular applications such as Premiere, Winamp, VirtualDub and DirectShow. Moreover, IGOL allows the automatic use of multiple cards to accelerate an application, demonstrated using DirectShow. To enable transparent acceleration without sacrificing performance, a three-tiered COM (Component Object Model) API has been designed and implemented. This API provides a well-defined and extensible interface which facilitates the development of hardware data processors that can accelerate multiple applications.
Quality, functionality and time-to-market are key indices for a competitive and successful embedded system product. A good way to reduce the time to market is to make use of reusable software models and reconfigurable...
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ISBN:
(纸本)0819446467
Quality, functionality and time-to-market are key indices for a competitive and successful embedded system product. A good way to reduce the time to market is to make use of reusable software models and reconfigurable hardware platform. This paper introduces a reconfigurable platform, which is now being done for methodology research on rapid development of embedded systems. The effective design method and efficient implementation technology are formal reuse and reconfiguration. The reusability consideration is mainly the reuse frequency and the abstraction level of the application system, while the reconfigurability consideration mainly includes reconfiguration of function/architecture, hardware/software and interfaces. In view of these considerations, the paper describes three possibly reconfigurable architectures like DSP-FPGA, MCU-FPGA and DSP-MCU-FPGA architectures. To get these architectures, we can use reconfigurable data-path units and library-based interfaces. In terms of benefits, the paper not only introduces knowledge achieved from development of this platform, but also demonstrates how to use the platform to construct an orthogonal IP space for development of virtual IPs and virtual components.
A fault testing methodology for a cell-based self configurable hardware platform (the Cell Matrix) is described. Background on the Cell Matrix is given, including its amenability to use despite the presence of manufac...
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ISBN:
(纸本)0819446467
A fault testing methodology for a cell-based self configurable hardware platform (the Cell Matrix) is described. Background on the Cell Matrix is given, including its amenability to use despite the presence of manufacturing defects. The ability of cells within the Cell Matrix to isolate faulty regions is also described. A method for testing individual cells, based on an external test driver, is discussed. The benefits of locating this test driver inside the device under test are explained. A method is described for efficient, autonomous, robust creation of a network of self-testing structures (called Supercells) for parallel implementation and execution of this test driver. Sample tests are described, and their results are given, demonstrating the effectiveness and robustness of the testing methodology. A discussion of the research, including conclusions, is presented. Plans for future work are discussed.
In this paper, we develop energy-efficient designs for matrix multiplication on fpgas. To analyze the energy dissipation, we develop a high-level model using domain-specific modeling techniques. In this model, we iden...
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ISBN:
(纸本)0819446467
In this paper, we develop energy-efficient designs for matrix multiplication on fpgas. To analyze the energy dissipation, we develop a high-level model using domain-specific modeling techniques. In this model, we identify architecture parameters that significantly affect the total energy (system-wide energy) dissipation. Then, we explore design trade-offs by varying these parameters to minimize the system-wide energy. For matrix multiplication, we consider a uniprocessor architecture and a linear array architecture to develop energy-efficient designs. For the uniprocessor architecture, the cache size is a parameter that affects the I/O complexity and the system-wide energy. For the linear array architecture, the amount of storage per processing element is a parameter affecting the system-wide energy. By using maximum amount of storage per processing element and minimum number of multipliers, we obtain a design that minimizes the system-wide energy. We develop several energy-efficient designs for matrix multiplication. For example, for 6 x 6 matrix multiplication, energy savings of upto 52% for the uniprocessor architecture and 36% for the linear arrary architecture is achieved over an optimized library for Virtex-II FPGA from Xilinx.
This Volume 4525 of the conference proceedings contains 18 papers. Topics discussed include field programmable gate arrays, reconfigurable computers, algorithms, filters, network processors and flexible buffer managem...
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This Volume 4525 of the conference proceedings contains 18 papers. Topics discussed include field programmable gate arrays, reconfigurable computers, algorithms, filters, network processors and flexible buffer management.
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable proces...
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ISBN:
(纸本)0819442496
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurableprocessors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurableprocessors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.
Three kinds of basic Variable Length Decoder were implemented on Dynamically reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of...
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ISBN:
(纸本)0819442496
Three kinds of basic Variable Length Decoder were implemented on Dynamically reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of required resources for each Decoder was described. Especially, in Generated unique address method, the Variable Length Decoder circuit size on Dynamically reconfigurable Cell Array Processor was quite small.
With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution f...
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ISBN:
(纸本)0819442496
With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution for a given problem instance. fpgas can be used with run-time reconfiguration to dynamically customize a circuit. Optimizations leading to faster circuits and reduced logic can result. The paper discusses the implementation of a run-time parameterizable 2D Discrete Wavelet Transform core using the JBits tool suite. The motivation for such a core is discussed. as well the benefits afforded by dynamic circuit specialization.
作者:
Vasilko, MBournemouth Univ
Sch Design Engn & Comp Microelect Syst Res Grp Poole BH12 5BB Dorset England
This paper presents an example of using a reconfigurable systems CAD tool (DYNASTY Framework) for the design exploration of various configuration subsystems in a specific reconfigurabletechnology. Given a set of appl...
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ISBN:
(纸本)0819442496
This paper presents an example of using a reconfigurable systems CAD tool (DYNASTY Framework) for the design exploration of various configuration subsystems in a specific reconfigurabletechnology. Given a set of application domain benchmarks, it is possible to examine whether a selected device configuration subsystem provides performance suitable for the targeted application domain. The approach is based on a 'plug-in' technology server, implemented in the DYNASTY Framework. which allows for many different configuration subsystems to be modelled at high level. The feasibility of using a specific configuration subsystem for the selected application domain can be assessed without the need to produce transistor-level device models. As an example, the paper presents an evaluation of partial reconfiguration performance for a simple design with two arithmetic modules. The design reconfiguration performance is evaluated for three different configuration subsystems (parallel random-access, frame-based and context-switched) implemented on top of the Xilinx XC6200 device architecture.
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