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检索条件"任意字段=Reconfigurable Technology: FPGAs and Reconfigurable Processors Computing and Communications IV"

共 41 条记录，以下是31-40 订阅

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Model-based performance analysis for reconfigurable coprocessors

Model-based performance analysis for reconfigurable coproces...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Charlwood, SM Mangnall, JP Quigley, SF Univ Birmingham Digital Syst & Vis Proc Grp Birmingham W Midlands England

ISBN: (纸本)0819442496

Uni-processor and shared memory UMA multi-processor workstations are currently ubiquitous. The capabilities of such machines are commonly extended through the use of one or more application-specific coprocessors, located on the system expansion/peripheral bus, or a dedicated local bus. It is therefore considered worthwhile to investigate the limits of applicability of FPGA-based reconfigurable coprocessors when used to enhance such machines. In order to do this, it must be possible to estimate performance for coprocessor architectures that do not currently exist. This paper describes a method for generating estimates of performance for applications which make use of such reconfigurable coprocessors. By combining direct measurements on the target platform with model-based estimates and simulation data, estimates of performance can be synthesised which are accurate to better than +/-5%.

关键词： model-based performance analysis software acceleration reconfigurable coprocessors

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Transformation from c-program to circuitry for a dynamically reconfigurable cell array processor

Transformation from c-program to circuitry for a dynamically...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Morihsita, T Komoku, K Hatano, F Teramoto, I Okayama Prefectural Univ Dept Comp Sci & Syst Engn Okayama 7191197 Japan

ISBN: (纸本)0819442496

We have been developing a parallel processor that it is possible to reconfigure hardware according to a software. Dynamic Reconfiguration means to change a kind of and a number of processing elements and connection between processing elements at real time. Our proposed processor creates a very long pipeline, which is able to execute for-loop calculation at very high speed. In this paper, we develop an algorithm which transform automatically a c-language program to a circuit diagram. Especially, we consider processing method of if-sentence and for-sentence and realize high-performance processing of them by a pipeline processing. The automatic transforming program is created by c-language. Finally, we examine a performance of this processor by using a MPEG decoding program.

关键词： reconfigurable architecture parallel processor auto-generation of circuitry dynamically reconfigurable processor

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Spatially reconfigurable module for FIR filters

Spatially reconfigurable module for FIR filters

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Plaks, TP S Bank Univ SCISM London SE1 0AA England

ISBN: (纸本)0819442496

This paper presents a spatially reconfigurable program module for FIR filter that can be used in FPGA design. Such a module is highly scalable and parameterized. In general, such program module describes classical probe Im size dependent arrays, fixed size arrays and arrays with increased performance. In the last case the problem is mapped into higher-dimensional array. As a theoretical basis we will use the theory of regular arrays. Efficient reconfiguring requires the rewriting of algorithms using algebraic transformations. For this purpose we will use the partitioning and specific pipe-structures. We will also use multi-dimensional time to increase the range of different array topologies. The description of a module includes pre scheduled designs, so, the reconfiguring does not require solving integer linear programming problems, and thus, can be used at run-time. The paper presents a family of scalable array structures for FIR filter: I-D, 2-D and 3-D structures with different input/output positioning and performance.

关键词： reconfigurable modules regular arrays FIR filter module description scalability

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Highly reconfigurable communication protocol multiplexing element for SCOPH

Highly reconfigurable communication protocol multiplexing el...

引用

Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Brebner, G Univ Edinburgh Div Informat Edinburgh Midlothian Scotland

ISBN: (纸本)0819442496

The Soft Circuitry Optimised Protocol Harness (SCOPH) project is concerned with implementing streaming data paths that perform communication protocol functions. The data paths are implemented dynamically using soft circuitry on a programmed logic array, based upon a small set of parameterised function blocks that are instantiated and linked together on a per-connection basis, and may also be modified during connections. This allows the use of optimised bespoke protocols, with handling of protocol functions at hardware speeds. This paper focuses on one particular pair of function blocks, for the demultiplexing and multiplexing of multiple connections sharing a single communication channel. An example would be multiple TCP port connections simultaneously active over a single IP channel. In the SCOPH context, a single data stream emanating from a main processor or from a network interface would be split into multiple data streams, which undergo protocol processing, and are then recombined into a single stream to a network interface or main processor respectively. The demultiplexor block always requires a means of selecting one of a number of streams, given addressing information in the data stream itself. Symmetrically, the multiplexor block must insert appropriate addressing information into the data stream. However, the main thrust of the paper is in comparing area-time trade-offs between using blocks with a (small) fixed number of streams always configured and using blocks that vary in size and shape with the current number of active streams. Both options are being investigated on a Xilinx Virtex FPGA, using JBits for the dynamic configuration.

关键词： reconfigurable computing communication protocols

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Signal processing for multiuser wireless systems on reconfigurable platforms

Signal processing for multiuser wireless systems on reconfig...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Thomas, J Syst Res Inst College Pk MD 20742 USA

ISBN: (纸本)0819442496

Iterative multiuser decoding (IMD) is a suboptimal reception technique that yields near-optimal performance via the iterative exchange of soft information between a (multiuser) demodulator and a bank of single-user soft decoders to their mutual benefit. Rom a practical perspective, using the minimum mean square error (MMSE) multiuser interference suppressor for demodulation yields good performance and near-far resistance over a wide range of received signal powers, in both additive white Gaussian noise and dispersive fading channels. The computational issues and system tradeoffs, involved in realizing MMSE-IMD receivers on reconfigurable platforms, at base stations in the multicell code-division multiple access (CDMA) uplink, are considered in this paper. In particular, an approximation is proposed, to reduce the complexity of the most computationally intensive task in the receiver, viz., the inversion of a matrix of dimensions proportional to the product of the spreading factor and the receiver sensor-count;this approximation is observed to degrade system performance only marginally. A suitable partitioning of the receiver's computational tasks between software- and hardware-configurable platforms is also proposed. This is followed by a study of the performance-complexity tradeoffs among various system design options (such as the iteration-count, receiver sensor-count, and choice of soft decoding algorithm) in such rapidly configurable environments, and their impact on system capacity. It is inferred that actual realizations of the MMSE-IMD can indeed provide vast performance gains over existing suboptimal receivers.

关键词： CDMA multicell networks iterative multiuser decoding multisensor receivers MMSE multiuser interference suppression reconfigurable architectures

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Programming high performance reconfigurable computers

Programming high performance reconfigurable computers

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Smith, MC Peterson, GD Univ Tennessee Dept Elect & Comp Engn Knoxville TN 37996 USA

ISBN: (纸本)0819442496

High Performance Computers (HPC) provide dramatically improved capabilities for a number of defense and commercial applications, but often are too expensive to acquire and to program. The smaller market and customized nature of HPC architectures combine to increase the cost of most such platforms. To address the problems with high hardware costs. one may create more inexpensive Beowolf clusters of dedicated commodity processors. Despite the benefit of reduced hardware costs. programming the HPC platforms to achieve high performance often proves extremely time-consuming and expensive in practice. In recent years. programming productivity gains come from the development of common APIs and libraries of functions to support distributed applications. Examples include PVM, MPI, BLAS, and VSIPL. The implementation of each API or library is optimized for a given platform. but application developers can write code that is portable across specific HPC architectures. The application of reconfigurable computing (RC) into HPC platforms promises significantly enhanced performance and flexibility at a modest cost. Unfortunately. configuring (programming) the reconfigurable computing nodes remains a challenging task and relatively little work to date has focused on potential high performance reconfigurable computing (HPRC) platforms consisting of reconfigurable nodes paired with processing nodes. This paper addresses the challenge of effectively exploiting HPRC resources by first considering the performance evaluation and optimization problem before turning to improving the programming infrastructure used for porting applications to HPRC platforms.

关键词： high performance computing reconfigurable computing programming performance evaluation

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Temporal partitioning of circuits for advanced partially reconfigurable systems

Temporal partitioning of circuits for advanced partially rec...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Mohan, R Dasu, A Panchanathan, S Arizona State Univ Dept Comp Sci & Engn Collaborat Program Ubiquitous Comp CUbiC Tempe AZ 85287 USA

ISBN: (纸本)0819442496

reconfigurable architectures are proving to be very effective in applications that involve the implementation of multiple compute-intensive algorithms, which share the same computing modules. With the advent of dynamically reconfigurable architectures, many temporal partitioning algorithms (TPA) have been proposed address the issue of area and time constraints. The main objective of TPA is to divide a large design into smaller sub-components so that they can be implemented over multiple reconfigurations. In this paper, we propose a new temporal partitioning process (TPP), which includes a modified TPA along with a port reallocation algorithm (PRA) to reduce the reconfiguration time to facilitate real-time implementation. The reduction in reconfiguration time is achieved by employing the knowledge of the function implemented in each logic block thereby effectively reusing the cells in the array in a selective manner. This avoids the need for complete reconfiguration and reduces the net reconfiguration time. The proposed approach has been tested on random graphs and on the MCNC benchmark circuits. Significant reduction in reconfiguration time has been achieved.

关键词： Logic Computer architecture Field programmable gate arrays Algorithm development Software Composites Computer engineering Computer science computing systems Multimedia

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XHWIF: A portable hardware interface for reconfigurable computing

XHWIF: A portable hardware interface for reconfigurable comp...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Sundararajan, P Guccione, SA Levi, D Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)0819442496

As the interest in FPGA-based hardware has grown, so has the number and type of commercially available platforms. The greatest drawback to this proliferation of hardware platforms is the lack of standards. Even boards using identical hosts, FPGA devices and bus interfaces typically have widely varying software interfaces, limiting the portability of tools and applications across these platforms. Xilinx's XHWIF(tm) portable hardware interface attempts to address this problem. The XHWIF interface provides a software layer providing all necessary communication and control for generic FPGA-based hardware. This interface permits tools and applications to be run on a variety of platforms, typically without modifications or re-compilation. In addition, a remote network interface is supplied as part of XHWIF API. Applications and tools which use the XHWIF interface can also run transparently across a network without modification. This permits not only sharing of hardware resources in a networked environment, but a simple way of implementing systems which use Remote Network Reconfiguration. XHWIF API is currently provided as part of Xilinx's JBits(tm) Software Development Kit.

关键词： FPGA reconfigurable computing hardware interface

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A real-time debugger with bitstream configurator & 'C' language design control for fpgas

A real-time debugger with bitstream configurator & 'C' langu...

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Conference on reconfigurable technology - fpgas and reconfigurable processors for computing and communications III

作者： Casselman, S Schewel, J Wartel, F Virtual Comp Corp Reseda CA 91335 USA

ISBN: (纸本)0819442496

At the boundary between hardware and software, where fpgas with 2,000,000 gates is just the beginning, we've found that the tools you have in your toolbox make all the difference. With larger and more feature rich programmable devices such as the Virtex (TM) Platform FPGA [1,2,3], even minors changes in the design can require hours of compile time. The combination of design complexity and component size is taxing current design entry and implementation tools, making the design cycle longer. The simulation-verification cycle doesn't mean the design will work in the final product. The engineer needs more than ever, to debug designs within the target hardware in real-time. We have built a series of integrated tools aimed at enhancing productivity at the last stages of product design, the final ten percent of the design that takes ninety percent of the time. The tools shown are not meant to replace current tools. These are advanced tools for the FPGA power user. Our goal is creating a set of tools specifically designed to provide better design control, dramatically reduce iteration times and enable real-time In-Circuit debugged in hardware. We have organized this series of tools as The technology Stack (TM).

关键词： bitstream emulator reconfigurable computers FPGA hardware software co-design HOT C to hardware

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Adaptive FIR filter design and implementation empowered by reconfigurable fpgas

Adaptive FIR filter design and implementation empowered by r...

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Visual communications and Image Processing 2000

作者： Dawood, Anwar Bergmann, Neil Asdani, Zulfi Bravo, Boris Queensland Univ of Technology Brisbane Australia

This paper explores the design and implementation of an adaptive Finite Impulse Response (FIR) Filter on reconfigurable computing technology (RCT). RCT deploys Field Programmable Gate Array (FPGA) technology as a flexible platform for implementing and improving digital systems design. Filters are used in data conditioning environments between transducers and digital systems for many industrial applications such as aerospace, telecommunications, and computers. They are one of the most demanding applications for changing operation requirements, in terms of data size, functionality and noise ratio. This study takes advantage of the flexibility and adaptability of the emerging fpgas technology for such applications. The deployment of an FPGA for filter design and implementation represents the most promising solution for changing operation requirements as compared to other solutions including the use of dedicated DSP processors. The paper describes the methodology followed throughout the analysis, design, verification, simulation, and implementation of the filter. It also elaborates on the scalability of the proposed design to more complex functions, higher resolution data, and variations in building arithmetic functions.

关键词： Optical filters

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