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BiDSRS plus : Resource Efficient reconfigurable Real Time Bidirectional Super Resolution System for fpgas

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2025年第1期15卷 120-132页

作者： Al Amin, Rashed Obermaisser, Roman Univ Siegen Inst Embedded Syst D-57076 Siegen Germany

Super-resolution (SR) systems represent a rapidly advancing area within Information and Communication technology (ICT) due to their significant applications in computer vision and visual communication. Integrating SR systems with Deep Neural Networks (DNNs) is a widely adopted method for leveraging faster and improved image reconstruction. However, the real-time computational demands, extensive energy overhead and the huge memory footprints associated with DNN-based SR systems limit their throughput and scalability. Field-programmable gate arrays (fpgas) present a viable and promising solution for exploring the structure and architecture of SR systems due to their reconfigurable nature and parallel computing capabilities. The existing FPGA-based solutions can effectively reduce the computational latency in SR systems, they often result in higher resource and energy consumption. Besides, the traditional SR techniques generally focus on either upscaling or downscaling images or videos without offering any scaling reconfigurability. To address these limitations, this paper introduces BiDSRS+, a novel FPGA based resource-efficient and reconfigurable real-time SR system using modified bicubic interpolation method. In addition, BiDSRS+ supports both upscaling and downscaling of images and videos, enhancing its versatility. Evaluations conducted on the Xilinx ZCU 102 FPGA board reveal substantial resource savings, with reductions of 44x LUT, 31x BRAM, and 35x DSP utilization compared to state-of-the-art DNN-based SR systems, albeit with a trade-off in throughput of 0.5x. Furthermore, when compared to leading algorithm-based SR systems, BiDSRS+ achieves reductions of 5.8x LUT, 1.75x BRAM, and 2.3x Power consumption, without compromising the throughput. Due to its high resource efficiency and reconfigurability with a throughput of 4K@60 FPS, BiDSRS+ offers significant advantages in promoting sustainable and energy-efficient green video communication.

关键词： Bicubic interpolation fpgas reconfigurable reconfigurable super-resolution super-resolution super-resolution

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A Survey on Architectures, Hardware Acceleration and Challenges for In-Network computing

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2025年第1期18卷 1-34页

作者： Nickel, Matthias Goehringer, Diana Tech Univ Dresden Dresden Germany Tech Univ Dresden Ctr Tactile Internet Human Loop CeTI Dresden Germany

By moving data and computation away from the end user to more powerful servers in the cloud or to cloudlets at the edge, end user devices only need to compute locally for small amounts of data and when low latency is required. However, with the advent of 6G and Internet-of-Everything, the demand for more powerful networks continues to grow. The introduction of Software-Defined Networking and Network Function Virtualization has allowed us to rethink networks and use them for more than just routing data to servers. In addition, the use of more powerful network devices is bringing new life to the concept of active networks in the form of in-network computing. In-Network computing provides the ability to move applications into the network and process data on programmable network devices as they are transmitted. In this work, we provide an overview of in-network computing and its enabling technologies. We take a look at the programmability and different hardware architectures for SmartNICs and switches, focusing primarily on accelerators such as fpgas. We discuss the state of the art and challenges in this area, and look at CGRAs, a class of hardware accelerators that have not been widely discussed in this context.

关键词： In-Network computing Software-Defined Networking FPGA CGRA SoC

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks defined eFPGA Design 38

Meta-Heuristic Optimization of Custom Heterogeneous Blocks d...

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38th International Conference on VLSI Design and International Conference on Embedded Systems

作者： Bhargav, D., V Pradyumna, G. Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798331522452;9798331522445

Modern Field-Programmable Gate Arrays (fpgas) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, fpgas are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). The proposed work employs Non-dominated Sorting Genetic Algorithm-ii (NSGA-ii) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable Logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. The results showed a significant improvement of 44.62% in hardware parameters.

关键词： eFPGA VTR OpenFPGA NSGA-ii Secure Silicon FPGA Layout reconfigurable computing

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Near-memory computing on fpgas with 3D-stacked Memories: applications, Architectures, and Optimizations

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2023年第1期16卷 1-32页

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Adapt Dynam Syst Nothnitzer Str 46 D-01062 Dresden Germany German Univ Cairo Elect Dept Cairo 11835 Egypt Tech Univ Darmstadt Merckstr 25 D-64283 Darmstadt Germany

The near-memory computing (NMC) paradigm has transpired as a promising method for overcoming the memory wall challenges of future computing architectures. Modern systems integrating 3D-stacked DRAM memory can be leveraged to prevent unnecessary data movement between the main memory and the CPU. FPGA vendors have started introducing 3D memories to their products in an effort to remain competitive on bandwidth requirements of modern memory-intensive applications. Recent NMC proposals target various types of data processing workloads such as graph processing, MapReduce, sorting, machine learning, and database analytics. In this article, we conduct a literature survey on previous proposals of NMC systems on fpgas integrated with 3D memories. By leveraging the high bandwidth offered from such memories together with specifically designed hardware, FPGA architectures have become a competitor to GPU solutions in terms of speed and energy efficiency. Various FPGA-based NMC designs have been proposed with software and hardware optimization methods to achieve high performance and energy efficiency. Our review investigates various aspects of NMC designs such as platforms, architectures, workloads, and tools. We identify the key challenges and open issues with future research directions.

关键词： Near-memory computing 3D stacking FPGA architectures high-bandwidth memory

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reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach 20th

Reconfigurable Edge Hardware for Intelligent IDS: Systematic...

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20th International Symposium on Applied reconfigurable computing (ARC)

作者： Foudhaili, Wadid Nechi, Anouar Thermann, Celine Al Johmani, Mohammad Buchty, Rainer Berekovic, Mladen Mulhem, Saleh Univ Lubeck Inst Comp Engn ITI Lubeck Germany

ISBN: (纸本)9783031556722;9783031556739

Intrusion detection systems (IDS) are crucial security measures nowadays to enforce network security. Their task is to detect anomalies in network communication and identify, if not thwart, possibly malicious behavior. Recently, machine learning has been deployed to construct intelligent IDS. This approach, however, is quite challenging particularly in distributed, highly dynamic, yet resource-constrained systems like Edge setups. In this paper, we tackle this issue from multiple angles by analyzing the concept of intelligent IDS (I-IDS) while addressing the specific requirements of Edge devices with a special focus on reconfigurability. Then, we introduce a systematic approach to constructing the I-IDS on reconfigurable Edge hardware. For this, we implemented our proposed IDS on state-of-the-art Field Programmable Gate Arrays (fpgas) technology as (1) a purely FPGA-based dataflow processor (DFP) and (2) a co-designed approach featuring RISC-V soft-core as FPGA-based soft-core processor (SCP). We complete our paper with a comparison of the state of the art (SoA) in this domain. The results show that DFP and SCP are both suitable for Edge applications from hardware resource and energy efficiency perspectives. Our proposed DFP solution clearly outperforms the SoA and demonstrates that required high performance can be achieved without prohibitively high hardware costs. This makes our proposed DFP suitable for Edge-based high-speed applications like modern communication technology.

关键词： Intrusion detection system Reconfigurabile Hardware Edge Device FPGA-based RISC-V Soft-Core

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FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2023年第4期16卷 1-32页

作者： Nechi, Anouar Groth, Lukas Mulhem, Saleh Merchant, Farhad Buchty, Rainer Berekovic, Mladen Univ Lubeck Inst Comp Engn Ratzeburger Allee 160 D-23562 Lubeck Germany Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Kopernikusstr 16 D-52074 Aachen Germany Newcastle Univ Sch Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

Recently, artificial intelligence applications have become part of almost all emerging technologies around us. Neural networks, in particular, have shown significant advantages and have been widely adopted over other approaches in machine learning. In this context, high processing power is deemed a fundamental challenge and a persistent requirement. Recent solutions facing such a challenge deploy hardware platforms to provide high computing performance for neural networks and deep learning algorithms. This direction is also rapidly taking over the market. Here, fpgas occupy the middle ground regarding flexibility, reconfigurability, and efficiency compared to general-purpose CPUs, GPUs, on one side, and manufactured ASICs on the other. FPGA-based accelerators exploit the features of fpgas to increase the computing performance for specific algorithms and algorithm features. Filling a gap, we provide holistic benchmarking criteria and optimization techniques that work across several classes of deep learning implementations. This article summarizes the current state of deep learning hardware acceleration: More than 120 FPGA-based neural network accelerator designs are presented and evaluated based on a matrix of performance and acceleration criteria, and corresponding optimization techniques are presented and discussed. In addition, the evaluation criteria and optimization techniques are demonstrated by benchmarking ResNet-2 and LSTM-based accelerators.

关键词： Deep learning fpgas inference accelerators

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly applications on fpgas

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2022年第2期15卷 1–33页

作者： Asiatici, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci EPFL IC IINFCOM LAP INF 137Batiment INFStn 14 CH-1015 Lausanne Switzerland

applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on fpgas due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24x area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

关键词： High performance computing reconfigurable computing nonblocking caches DRAM cuckoo hashing irregular memory accesses

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A reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

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IEEE ACCESS 2023年 11卷 59438-59445页

作者： Kim, Victoria Heekyung Choi, Kyuwon Ken IIT Dept Elect & Comp Engn Chicago IL 60616 USA

In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile fpgas such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, an

关键词： INDEX TERMS FPGA accelerator CNN accelerator RT level design techniques low power techniques reconfigurable accelerator CNN-based object detection low power consumption high performance mobile FPGA

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A reconfigurable Approximate computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS ii-EXPRESS BRIEFS 2023年第1期70卷 291-295页

作者： Liu, Bo Xue, Anfeng Wang, Ziyu Xie, Na Wang, Xuetao Wang, Zhen Cai, Hao Southeast Univ Natl ASIC Syst Engn Ctr Nanjing 210096 Peoples R China Nanjing Prochip Elect Technol Co Ltd Nanjing 210001 Peoples R China

Approximate computing (AC) is an innovative paradigm for error-resilient signal processing applications. Addition is often a fundamental function for many of these applications. Particularly, binarized weight network (BWN) eliminates the multiplication by quantizing the weight to 1 bit, and the convolution can be achieved by simple accumulation. To further improve the energy efficiency of BWN, an approximate computing architecture based on the reconfigurable approximate adder with dual-VDD is proposed. The precision of the proposed approximate addition structure can be configured by setting approximate bit-width (ABW), and different voltage supplies can be configured for the approximate adder to reduce power consumption. A keywords-spotting (KWS) processor based on an optimized BWN is then used as a case study of the proposed approximate computing architecture. Implemented and evaluated under 22nm technology, the power consumption of the proposed BWN accelerator can be reduced by 54.3%, while the accuracy loss is only 0.4%.

关键词： Adders Power demand Energy efficiency Approximate computing Computer architecture Speech recognition Delays Approximate computing binarized weight network approximate adder keywords-spotting

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Performance Modeling and Scalability Analysis of Stream computing in ESSPER FPGA Clusters 22

Performance Modeling and Scalability Analysis of Stream Comp...

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22nd International Conference on Field Programmable technology (ICFPT)

作者： Miyagi, Ryota Yasudo, Ryota Sano, Kentaro Takase, Hideki Univ Tokyo Tokyo Japan Kyoto Univ Kyoto Japan RIKEN Kobe Hyogo Japan

ISBN: (纸本)9798350359114

ESSPER is a flexible and scalable FPGA cluster system designed for reconfigurable HPC, with customizability, scalability, and interoperability with existing HPC systems. The inherent characteristics of ESSPER make it a superior alternative for achieving highly scalable computing solutions, particularly for compute-intensive applications such as numerical simulations and machine learning. However, constraints in communication bandwidth or latency can impact performance and scalability. This paper builds upon a previous performance model study to analyze performance modeling and scalability of streaming computation using a 1D ring of cascaded fpgas with high-speed, low-latency communication links in ESSPER. For evaluation and verification, we implemented a simple vector addition on ESSPER. The Result indicates that measured performance metrics closely align with predictions from the performance model. This model can also be used to estimate performance for other ESSPER applications.

关键词： streaming computing scalability multiple fpgas high-performance computing.

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