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parallel Computing: Accelerating Computational Science and Engineering (CSE) 1

引用

丛书名： Advances in parallel Computing, volume 25

2014年

作者： Bader, Michael

ISBN: (数字)9781614993810

ISBN: (纸本)9781614993803;9781614993810

parallel computing has been the enabling technology of high-end machines for many years. Now, it has finally become the ubiquitous key to the efficient use of any kind of multi-processor computer architecture, from smart phones, tablets, embedded systems and cloud computing up to exascale computers. This book presents the proceedings of ParCo2013 – the latest edition of the biennial international Conference on parallel Computing – held from 10 to 13 September 2013, in Garching, Germany. The conference focused on several key parallel computing areas. Themes included parallel programming models for multi- and manycore CPUs, GPUs, FPGAs and heterogeneous platforms, the performance engineering processes that must be adapted to efficiently use these new and innovative platforms, novel numerical algorithms and approaches to large-scale simulations of problems in science and engineering. The conference programme also included twelve mini-symposia (including an industry session and a special PhD symposium), which comprehensively represented and intensified the discussion of current hot topics in high performance and parallel computing. These special sessions covered large-scale supercomputing, novel challenges arising from parallel architectures (multi-/manycore, heterogeneous platforms, FPGAs), multi-level algorithms as well as multi-scale, multi-physics and multi-dimensional problems. It is clear that parallel computing – including the processing of large data sets (“Big Data”) – will remain a persistent driver of research in all fields of innovative computing, which makes this book relevant to all those with an interest in this field.

关键词： parallel processing (Electronic computers)--Congresses

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It's About Time: On Optimal Virtual Network Embeddings under Temporal Flexibilities

It's About Time: On Optimal Virtual Network Embeddings under...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Matthias Rost Stefan Schmid Anja Feldmann Internet Network Architectures Technische Universitat Berlin Germany Telekom Innovation Laboratories Germany

Distributed applications often require high-performance networks with strict connectivity guarantees. For instance, many cloud applications suffer from today's variations of the intra-cloud bandwidth, which leads to poor and unpredictable application performance. Accordingly, we witness a trend towards virtual networks (VNets) which can provide resource isolation. Interestingly, while the problem of where to embed a VNet is fairly well-understood today, much less is known about when to optimally allocate a VNet. This however is important, as the requirements specified for a VNet do not have to be static, but can vary over time and even include certain temporal flexibilities. This paper initiates the study of the temporal VNet embedding problem (TVNEP). We propose a continuous-time mathematical programming approach to solve the TVNEP, and present and compare different algorithms. Based on these insights, we present the CSM-Model which incorporates both symmetry and state-space reductions to significantly speed up the process of computing exact solutions to the TVNEP. Based on the CSM-Model, we derive a greedy algorithm OGA to compute fast approximate solutions. In an extensive computational evaluation, we show that despite the hardness of the TVNEP, the CSM-Model is sufficiently powerful to solve moderately sized instances to optimality within one hour and under different objective functions (such as maximizing the number of embeddable VNets). We also show that the greedy algorithm exploits flexibilities well and yields good solutions. More generally, our results suggest that already little time flexibilities can improve the overall system performance significantly.

关键词： Substrates Resource management Computational modeling Bandwidth Abstracts Linear programming Mathematical model

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Towards Transparent parallel/Distributed Support for Real-Time Embedded Applications

Towards Transparent Parallel/Distributed Support for Real-Ti...

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8th IEEE international symposium on Industrial Embedded Systems (SIES)

作者： Garibay-Martinez, Ricardo Ferreira, Luis Lino Maia, Claudio Pinho, Luis Miguel Polytech Inst Porto ISEP CISTER INESC TEC Oporto Portugal

ISBN: (纸本)9781479906581

An increasing number of real-time embedded applications present high computation requirements which need to be realized within strict time constraints. Simultaneously, architectures are becoming more and more heterogeneous, programming models are having difficulty in scaling or stepping outside of a particular domain, and programming such solutions requires detailed knowledge of the system and the skills of an experienced programmer. In this context, this paper advocates the transparent integration of a parallel and distributed execution framework, capable of meeting real-time constraints, based on OpenMP programming model, and using MPI as the distribution mechanism. The paper also introduces our modified implementation of GCC compiler, enabled to support such parallel and distributed computations, which is evaluated through a real implementation. This evaluation gives important hints, towards the development of the parallel/distributed fork-join framework for supporting real-time embedded applications.

关键词： parallel execution real-time distributed embedded systems compiler support GCC OpenMP MPI

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INSPIRE The Insieme parallel Intermediate Representation

INSPIRE The Insieme Parallel Intermediate Representation

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22nd international Conference on parallel architectures and Compilation Techniques (PACT)

作者： Jordan, Herbert Pellegrini, Simone Thoman, Peter Kofler, Klaus Fahringer, Thomas Univ Innsbruck Inst Comp Sci A-6020 Innsbruck Austria

ISBN: (纸本)9781479910212

programming standards like OpenMP, OpenCL and MPI are frequently considered programming languages for developing parallel applications for their respective kind of architecture. Nevertheless, compilers treat them like ordinary APIs utilized by an otherwise sequential host language. Their parallel control flow remains hidden within opaque runtime library calls which are embedded within a sequential intermediate representation lacking the concepts of parallelism. Consequently, the tuning and coordination of parallelism is clearly beyond the scope of conventional optimizing compilers and hence left to the programmer or the runtime system. The main objective of the Insieme compiler is to overcome this limitation by utilizing INSPIRE, a unified, parallel, high-level intermediate representation. Instead of mapping parallel constructs and APIs to external routines, their behavior is modeled explicitly using a unified and fixed set of parallel language constructs. Making the parallel control flow accessible to the compiler lays the foundation for the development of reusable, static and dynamic analyses and transformations bridging the gap between a variety of parallel paradigms. Within this paper we describe the structure of INSPIRE and elaborate the considerations which influenced its design. Furthermore, we demonstrate its expressiveness by illustrating the encoding of a variety of parallel language constructs and we evaluate its ability to preserve performance relevant aspects of input codes.

关键词： Compiler Intermediate Representation parallel Computation High-level Program Analysis

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YAPPA: a Compiler-Based parallelization Framework for Irregular Applications on MPSoCs

YAPPA: a Compiler-Based Parallelization Framework for Irregu...

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international symposium on Rapid System Prototyping / Embedded Systems Week

作者： Lovergine, Silvia Tumeo, Antonino Villa, Oreste Ferrandi, Fabrizio Pacific NW Natl Lab Richland WA 99352 USA Politecn Milan DEIB Milan Italy

ISBN: (纸本)9781479924097

Modern embedded systems include hundreds of cores. Because of the difficulty in providing a fast, coherent memory architecture, these systems usually rely on non-coherent, non-uniform memory architectures with private memories for each core. However, programming these systems poses significant challenges. The developer must extract large amounts of parallelism, while orchestrating communication among cores to optimize application performance. These issues become even more significant with irregular applications, which present data sets difficult to partition, unpredictable memory accesses, unbalanced control flow and fine grained communication. Hand-optimizing every single aspect is hard and time-consuming, and it often does not lead to the expected performance. There is a growing gap between such complex and highly-parallel architectures and the high level languages used to describe the specification, which were designed for simpler systems and do not consider these new issues. In this paper we introduce YAPPA (Yet Another parallel programming Approach), a compilation framework for the automatic parallelization of irregular applications on modern MPSoCs based on LLVM. We start by considering an efficient parallel programming approach for irregular applications on distributed memory systems. We then propose a set of transformations that can reduce the development and optimization effort. The results of our initial prototype confirm the correctness of the proposed approach.

关键词： Irregular Applications Compilers parallel Code Generation Embedded Systems HPC

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Implementing a Blocked Aasen's Algorithm with a Dynamic Scheduler on Multicore architectures

Implementing a Blocked Aasen's Algorithm with a Dynamic Sche...

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IEEE 27th international parallel and Distributed Processing symposium (IPDPS)

作者： Ballard, Grey Becker, Dulceneia Demmel, James Dongarra, Jack Druinsky, Alex Peled, Inon Schwartz, Oded Toledo, Sivan Yamazaki, Ichitaro Univ Tennessee Knoxville TN 37996 USA Tel Aviv Univ IL-69978 Tel Aviv Israel Univ Calif Berkeley Berkeley CA USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9780769549712

Factorization of a dense symmetric indefinite matrix is a key computational kernel in many scientific and engineering simulations. However, there is no scalable factorization algorithm that takes advantage of the symmetry and guarantees numerical stability through pivoting at the same time. This is because such an algorithm exhibits many of the fundamental challenges in parallel programming like irregular data accesses and irregular task dependencies. In this paper, we address these challenges in a tiled implementation of a blocked Aasen's algorithm using a dynamic scheduler. To fully exploit the limited parallelism in this left-looking algorithm, we study several performance enhancing techniques;e. g., parallel reduction to update a panel, tall-skinny LU factorization algorithms to factorize the panel, and a parallel implementation of symmetric pivoting. Our performance results on up to 48 AMD Opteron processors demonstrate that our implementation obtains speedups of up to 2.8 over MKL, while losing only one or two digits in the computed residual norms.

关键词： information retrieval matrix decomposition multiprocessing systems numerical stability parallel architectures parallel programming scheduling

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Modeling communication in cache-coherent SMP systems - A case study with Xeon Phi

Modeling communication in cache-coherent SMP systems - A cas...

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22nd ACM international symposium on High-Performance parallel and Distributed Computing, HPDC 2013

作者： Ramos, Sabela Hoefler, Torsten Computer Architecture Group University of A Coruña A Coruña Spain Scalable Parallel Computing Lab. ETH Zurich Zurich Switzerland

ISBN: (纸本)9781450319102

Most multi-core and some many-core processors implement cache coherency protocols that heavily complicate the design of optimal parallel algorithms. Communication is performed implicitly by cache line transfers between cores, complicating the understanding of performance properties. We developed an intuitive performance model for cache-coherent architectures and demonstrate its use with the currently most scalable cache-coherent many-core architecture, Intel Xeon Phi. Using our model, we develop several optimal and optimized algorithms for complex parallel data exchanges. All algorithms that were developed with the model beat the performance of the highly-tuned vendor-specific Intel OpenMP and MPI libraries by up to a factor of 4.3. The model can be simplified to satisfy the tradeoff between complexity of algorithm design and accuracy. We expect that our model can serve as a vehicle for advanced algorithm design. © 2013 ACM.

关键词： Electronic data interchange

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Architectural Support for Runtime Verification on ccNUMA Multiprocessors

Architectural Support for Runtime Verification on ccNUMA Mul...

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8th IEEE international Design and Test symposium (IDT)

作者： Nassar, Ahmed Kurdahi, Fadi J. Univ Calif Irvine Dept EECS Irvine CA 92697 USA

ISBN: (纸本)9781479935253

This paper presents a runtime verification (RV) framework on distributed shared-memory multiprocessors based on explicit functional/concurrency intent specification in the form of temporal logic properties. A generic programming model, that subsumes task and data parallelism, has been wrought along with an automata-based formulation of the RV problem. algorithms are implemented for the construction and minimization of automata checkers that can be executed concurrently with multithreaded applications to assert their correct functioning. The needed architectural supporting mechanisms and the ensuing design tradeoffs are investigated using an approximately-timed transaction-level model. The simulation model confirms scalability of the proposed RV approach to large multiprocessor systems. It also quantifies the increase in the number of processors needed to replenish the monitoring-induced performance degradation.

关键词： parallel architectures temporal logic software debugging automata shared memory systems distributed computing

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Generalized Hierarchical All-to-all Exchange Patterns

Generalized Hierarchical All-to-all Exchange Patterns

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IEEE 27th international parallel and Distributed Processing symposium (IPDPS)

作者： Prisacari, Bogdan Rodriguez, German Minkenberg, Cyriel IBM Res Ruschlikon Ruschlikon Switzerland

ISBN: (纸本)9780769549712

The personalized all-to-all collective exchange is one of the most challenging communication patterns in HPC applications in terms of performance and scalability. We present a framework for the design of optimized collective patterns for generic hierarchical topologies. Our proposal can be applied, among others, to two types of topologies of great importance today: (i) the family of extended generalized fat tree networks (including k-ary n-trees and their variations) which are extensively used today in both HPC and commercial data centers, and (ii) direct low-diameter scalable hierarchical architectures such as the recently proposed dragonfly networks. We argue that exchange patterns that are congruent with the underlying structure of the network have inherent advantages compared to patterns that are oblivious to this structure. However, the current commonly used hierarchical pattern, the XOR exchange, has limited applicability, because it requires that the number of communicating nodes equals an integral power of two, making it suitable only for few tree designs and unsuitable for any dragonfly network. We propose several new, generic, universally applicable approaches to perform such exchanges in a hierarchical fashion that outperform current state of the art approaches. We support our claims by means of both mathematical proofs and simulation results that show that we can achieve an improvement of almost two-fold in dragonflies, and a two-to three-fold improvement in fat tree networks in cases where the XOR exchange cannot be applied.

关键词： network topology parallel algorithms trees (mathematics)

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Scheduling parallel Programs by Work Stealing with Private Deques 13

Scheduling Parallel Programs by Work Stealing with Private D...

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18th ACM SIGPLAN symposium on Principles and Practice of parallel programming

作者： Acar, Umut A. Chargueraud, Arthur Rainey, Mike Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA Univ Paris 11 CNRS LRI Orsay France

ISBN: (纸本)9781450319225

Work stealing has proven to be an effective method for scheduling parallel programs on multicore computers. To achieve high performance, work stealing distributes tasks between concurrent queues, called deques, which are assigned to each processor. Each processor operates on its deque locally except when performing load balancing via steals. Unfortunately, concurrent deques suffer from two limitations: 1) local deque operations require expensive memory fences in modern weak-memory architectures, 2) they can be very difficult to extend to support various optimizations and flexible forms of task distribution strategies needed many applications, e. g., those that do not fit nicely into the divide-and-conquer, nested data parallel paradigm. For these reasons, there has been a lot recent interest in implementations of work stealing with non-concurrent deques, where deques remain entirely private to each processor and load balancing is performed via message passing. Private deques eliminate the need for memory fences from local operations and enable the design and implementation of efficient techniques for reducing task-creation overheads and improving task distribution. These advantages, however, come at the cost of communication. It is not known whether work stealing with private deques enjoys the theoretical guarantees of concurrent deques and whether they can be effective in practice. In this paper, we propose two work-stealing algorithms with private deques and prove that the algorithms guarantee similar theoretical bounds as work stealing with concurrent deques. For the analysis, we use a probabilistic model and consider a new parameter, the branching depth of the computation. We present an implementation of the algorithm as a C++ library and show that it compares well to Cilk on a range of benchmarks. Since our approach relies on private deques, it enables implementing flexible task creation and distribution strategies. As a specific example, we show how to impleme

关键词： work stealing nested parallelism dynamic load balancing

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