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检索条件"任意字段=Seventh International Symposium on Parallel Architectures, Algorithms and Programming"

共 511 条记录，以下是291-300 订阅

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A Distributed Dynamic parallel Algorithm for SIFT Feature Extraction

A Distributed Dynamic Parallel Algorithm for SIFT Feature Ex...

引用

international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Guiyuan Jiang Guiling Zhang Dakun Zhang School of Computer Science & Software Engineering Tianjin Professional University Tianjin China

This paper deals with the issue of developing efficient algorithms for accelerating SIFT (Scale Invariant Feature Transform) features extraction under distributed environment. The proposed distributed dynamic parallel algorithm (DDP-SIFT) using a special data parallel approach that divides the Gauss Scale Space by octave aimed at acquiring large image blocks which is of great importance in some application. To make this approach effective, steps of building Gauss Scale Space are changed, and only the prerequisite part which is only 1/13 of the whole pyramid will be produced before tasks allocation, and Allocation Data Quantity (ADQ) is decreased by 13 times. Data blocks are assembled as tasks maintained in task lists, and dynamically allocated to Computing Nodes. A refined-blocking approach is proposed to further improve load balance. Our investigations show that the proposed algorithm has remarkable performance on accelerating SIFT features extraction while pursuing large data blocks.

关键词： Feature extraction Heuristic algorithms Resource management Acceleration parallel algorithms Hardware Buildings

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Research and Design of a Remote Visualization parallel Program Performance Analysis Tool

Research and Design of a Remote Visualization Parallel Progr...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Yunlong Xu Zeng Zhao Weiguo Wu Yixin Zhao School of Electronics and Information Engineering Xi'an Jiaotong University Xi'an China

parallel program performance analysis plays an important role in exploring parallelism and improving efficiency of parallel programs. A remote interactive parallel program performance analysis tool based on dynamic code instrumentation is designed on the basis of analysis and comparison of existing program performance analysis tools. A hierarchical structure is adopted by this tool which consists of 3 parts: client, server and computing nodes. Performance analysis tasks are submitted to the server via the graphical user interface of the client, and then actual analysis processes are started on the computing nodes by the server to collect performance data for visualization in the client. The performance information gained by this tool is comprehensive and intuitive, so it is quite helpful for users to analyze performance, locate bottlenecks of programs, and optimize programs.

关键词： Performance analysis Data visualization Servers Instruments parallel processing Process control Computer architecture

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parallel Multisets Sorting Using Aperiodic Multi-round Distribution Strategy on Heterogeneous Multi-core Clusters

Parallel Multisets Sorting Using Aperiodic Multi-round Distr...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Cheng Zhong Zeng-Yan Qu Feng Yang Meng-Xiao Yin School of Computer and Electronics and Information Guangxi University Nanning China

To sort efficiently Multisets in parallel on the heterogeneous multi-core clusters that the nodes have different amount of processing cores, different computing and communication capabilities and distinct size of main memory, a novel a periodic multi-round data distribution model is presented and a parallel sorting algorithm for Multisets is designed by using the characteristics of multi-threading technology and multi-level caches on multi-core architectures. The first round scheduling assigns data blocks into the slave multi-core nodes according to the given distribution order, and the other rounds scheduling will distribute data blocks into the slave multi-core nodes by First Request First Distribution (FRFD) strategy to ensure that each slave multi-core node can receive the next required data block before it has sorting the current data block in its own main memory. The experimental results on the heterogeneous cluster with multi-core computers show that the presented parallel sorting Multisets algorithm is efficient and it obtains good speedup and scalability.

关键词： Sorting Algorithm design and analysis Clustering algorithms Multicore processing Memory management Distributed databases Nickel

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A Coherence of Ramsey Phenomena

A Coherence of Ramsey Phenomena

引用

international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Kai-Rui Wang Cheng-Xi Wang School of Informational Science Yunnan University Kunming China School of Mathematics Capital Normal University Bejing China

The restricted coexistence as an accumulated status or an idea can be used to explain why so-called Ramsey's effects or phenomena exist. From this, some properties, for instance, for all integers q≥ p≥3, a deep inequality R(p, q) ≥ R(p -1, q + 2), are proved, based on coherence of Ramsey's phenomena and the viewpoint of accumulated quantity. Further by known data, we declare finally two Ramsey numbers R(4, 7) = R(5, 5) = 49. The theory is so unusually stunning that it spreads rapidly to all science society and influences permanently people's views toward many problems from modern science and technology, such as celebrated NP-problem from computational complexity theory or theoretic computer, completeness of axiom systems from formal logic or foundation of mathematics, and so forth.

关键词： Coherence Educational institutions Upper bound Convergence Color programming

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The parallel Processing Based on CUDA for Convolution Filter FDK Reconstruction of CT

The Parallel Processing Based on CUDA for Convolution Filter...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Benyi Shi Sihai Chen Feifei Huang Cheng Wang Kun Bi College of Optoelectronic Science and Engineering Huazhong University of Science and Technology Wuhan China Beijing Research Center for Information Technology in Agriculture Beijing China

Computed tomography (CT) technology has been used in many fields. But the slow speed of CT image reconstruction is unbearable in some situation. The parallel processing based on graphic processing unit (GPU) is a great option to accelerate the speed of CT image reconstruction. But the general purpose GPU program model is difficult to use for the texture programming. Compute unified device architecture (CUDA) program model is much easier to use. A parallel processing based CUDA for CT image convolution filter FDK reconstruction was proposed in this article. The acceleration of FDK algorithm with convolution filtering on a single GPU had been realized. Under the condition that the precision was assured, the speed of CT image reconstruction has been accelerated about 80 times in the kernel algorithm and about 11 times in the overall performance according to the experiment result.

关键词： Graphics processing unit Image reconstruction Computed tomography Instruction sets parallel processing Acceleration Kernel

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A Case Study of SWIM: Optimization of Memory Intensive Application on GPGPU

A Case Study of SWIM: Optimization of Memory Intensive Appli...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Wei Yi Yuhua Tang Guibin Wang Xudong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Recently, GPGPU has been adopted well in the High Performance Computing (HPC) field. The limited global memory bandwidth poses a great challenge to many GPGPU programmers trying to exploit parallelism within the CPU-GPU heterogeneous platform. In this paper, we choose SWIM, a typical memory intensive application from the SPEC OMP 2001 benchmark suite, for case study. We attempt to optimize the performance and energy consumption of the application utilizing different memory access mechanisms and present optimization methods including matrix transposition and kernel fusion. The experimental results on the Intel Core TM i920 CPU plus GeForce GTX 295 platform shows that, the proposed optimizing methods achieve a speedup of 8.7X over the original OpenMP program and reduce the energy consumption by 83% for the problem size of 2048*2048.

关键词： Instruction sets Kernel Bandwidth Graphics processing unit Memory management Energy consumption Central Processing Unit

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A Translation Framework for Virtual Execution Environment on CPU/GPU Architecture

A Translation Framework for Virtual Execution Environment on...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Guoxing Dong Kai Chen Erzhou Zhu Yichao Zhang Zhengwei Qi Haibing Guan School of Software Shanghai Jiaotong University Shanghai China School of Information Security Engineering Shanghai Jiaotong University Shanghai China Department of Computer Science and Engineering Shanghai Key Laboratory of Scalable Computing and Systems Shanghai Jiaotong University Shanghai China

GPUs are many-core processors with tremendous computational power. However, as automatic parallelization has not been realized yet, developing high-performance parallel code for GPUs is still very challenging. The paper presents a novel translation framework designed for virtual execution environment based on CPU/GPU architecture. It addresses two major challenges of taking advantage of general purpose computation on graphics processing units (GPGPU) to improve performance: no rewriting the existing source code and resolving binary compatibility issues between different GPUs. The translation framework uses semi-automatic parallelization technology to port existing code to explicitly parallel programming models. It not only offers a mapping strategy from X86 platform to CUDA programming model, but also synchronizes the execution between the CPU and the GPUs. The input to our translation framework is parallelizable part of the program within binary code. With an additional information related to the parallelizable part, the translation framework transforms the sequential code into PTX code and execute it on GPUs. Experimental results on several programs from CUDA SDK Code Samples and Parboil Benchmark Suite show that our translation framework could achieve very high performance, even up to several tens of times speedup over the X86 native version.

关键词： Graphics processing unit Registers Kernel Instruction sets Driver circuits programming Computer architecture

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Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips

Run-Time Partitioning of Hybrid Distributed Shared Memory on...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Xiaowen Chen Zhonghai Lu Axel Jantsch Shuming Chen Department of Electronic Systems KTH-Royal Institute of Technology Stockholm Sweden Institute of Microelectronic and Microprocessor National University of Defense Technology Changsha China

On multi-core Network-on-Chips (NoCs), memories are preferably distributed and supporting Distributed Shared Memory (DSM) is essential for the sake of reusing huge amount of legacy code and easy programming. However, the DSM organization imports the inherent overhead of translating virtual memory addresses into physical memory addresses, resulting in negative performance. We observe that, in parallel applications, different data have different properties (private or shared). For the private data accesses, it's unnecessary to perform Virtual-to-Physical address translations. Even for the same datum, its property may be changeable in different phases of the program execution. Therefore, this paper focuses on decreasing the overhead of Virtual-to-Physical address translation and hence improving the system performance by introducing hybrid DSM organization and supporting run-time partitioning according to the data property. The hybrid DSM organization aims at supporting fast and physical memory accesses for private data and maintaining a global and single virtual memory space for shared data. Based on the data property of parallel applications, the run-time partitioning supports changing the hybrid DSM organization during the program execution. It ensures fast physical memory addressing on private data and conventional virtual memory addressing on shared data, improving the performance of the entire system by reducing virtual-to-physical address translation overhead as much as possible. We formulate the run-time partitioning of hybrid DSM organization in order to analyze its performance. A real DSM based multi-core NoC platform is also constructed. The experimental results of real applications show that the hybrid DSM organization with run-time partitioning demonstrates performance advantage over the conventional DSM counterpart. The percentage of performance improvement depends on problem size, way of data partitioning and computation/communication ratio of parallel ap

关键词： Organizations Delay System performance programming Memory management System-on-a-chip Registers

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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Improved parameterized efficient FPGA implementations of par...

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IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Sami Hasan Said Boussakta Alex Yakovlev School of Electrical Electronic and Computer Engineering University of Newcastle UK

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. The improved parameterized FPGA implementation is a system-level abstraction of hardware-oriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time.

关键词： Delay Finite impulse response filter

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User level DB: a debugging API for user-level thread libraries

User level DB: a debugging API for user-level thread librari...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Kevin Pouget Marc Pérache Patrick Carribault Hervé Jourdren CEA DIF Arpajon France

ISBN: (纸本)9781424465330

With the advent of the multicore era, parallel programming is becoming ubiquitous. Multithreading is a common approach to benefit from these architectures. Hybrid M:N libraries like MultiProcessor Communication (MPC) or MARCEL reach high performance expressing fine-grain parallelism by mapping M user-level threads onto N kernel-level threads. However, such implementations skew the debuggers' ability to distinguish one thread from another, because only kernel threads can be handled. SUN MICROSYSTEMS' THREAD_DB API is an interface between the debugger and the thread library allowing the debugger to inquire for thread semantics details. In this paper we introduce the USER LEVEL DB (ULDB) library, an implementation of the THREAD_DB interface abstracting the common features of user-level thread libraries. ULDB gathers the generic algorithms required to debug threads and provide the thread library with a small and focused interface. We describe the usage of our library with widely-used debuggers (GDB, DBX) and the integration into a user-level thread library (GNUPTH) and two high-performance hybrid libraries (MPC, MARCEL).

关键词： Debugging Libraries Multithreading Kernel Clocks Multicore processing parallel programming parallel processing Surges

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