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检索条件"任意字段=Seventh International Symposium on Parallel Architectures, Algorithms and Programming"

共 505 条记录，以下是301-310 订阅

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Algorithm Transformation for FPGA Implementation

Algorithm Transformation for FPGA Implementation

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IEEE international Workshop on Electronic Design, Test and Applications (DELTA)

作者： Donald G. Bailey Christopher T. Johnston School of Engineering and Advanced Technology Massey University Palmerston North New Zealand

ISBN: (纸本)9781424460250;9780769539782

High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an efficient hardware architecture, one that makes use of the available parallelism, the algorithms need to be transformed. Eleven such transformations are identified and explained. While some of these are straightforward, and have been implemented by some compilers, many cannot be automated because they require detailed knowledge of the algorithm.

关键词： Field programmable gate arrays Computer architecture Image processing Algorithm design and analysis Hardware design languages Software algorithms parallel processing Acceleration Application software Electronic equipment testing

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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OSL: Optimized Bulk Synchronous parallel Skeletons on Distributed Arrays 1

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8th international symposium on Advanced parallel Processing Technologies

作者： Javed, Noman Loulergue, Frederic Univ Orleans LIFO F-45067 Orleans France

ISBN: (数字)9783642036446

ISBN: (纸本)9783642036439

The existing solutions to program parallel architectures range from parallelizing compilers to distributed concurrent programming Intermediate approaches propose a more structured parallelism. Algorithmic skeletons are higher-order functions that capture the patterns of parallel algorithms. The user of the library has just to compose some of the skeletons to write her parallel application. When one is designing a parallel program, the parallel performance is important. It is thus very interesting for the programmer to rely on a simple yet realistic parallel performance model such as the Bulk Synchronous parallel (BSP) model. We present OSL, the Orleans Skeleton Library of BSP algorithmic skeletons in C++. It offers data-parallel skeletons on arrays as well as communication oriented skeletons. The performance of OSL is demonstrated with two applications;heat equation and FFT.

关键词： C++ (programming language)

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8th international symposium on parallel and Distributed Computing, ISPDC 2009

8th International Symposium on Parallel and Distributed Comp...

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8th international symposium on parallel and Distributed Computing, ISPDC 2009

ISBN: (纸本)9780769536804

The proceedings contain 35 papers. The topics discussed include: dynamic job scheduling on heterogeneous clusters;throughput optimization for micro-factories subject to failures;multi-hop congestion control algorithm in mobile wireless networks;a dynamic model for fire emergency evacuation based on wireless sensor networks;CPU load prediction model for distributed computing;event-driven configuration of a neural network CMP system over a homogeneous interconnect fabric;parallel position weight matrices algorithms;coarse-grained loop parallelization: iteration space slicing vs affine transformations;on the performance of contention managers for complex transactional memory benchmarks;distributed causal model-based diagnosis based on interacting behavioral Petri Nets;programming abstractions and toolchain for dataflow multithreading architectures;and distributed shared memory for the cell broadband engine (DSMCBE).

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Autonomic management of non-functional concerns in distributed & parallel application programming

Autonomic management of non-functional concerns in distribut...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Marco Aldinucci Marco Danelutto Peter Kilpatrick Department Computer Science University of Torino Torino Italy Department Computer Science University of Pisa Pisa Italy Department Computer Science Queen''s University Belfast Belfast UK

ISBN: (纸本)9781424437511

An approach to the management of non-functional concerns in massively parallel and/or distributed architectures that marries parallel programming patterns with autonomic computing is presented. The necessity and suitability of the adoption of autonomic techniques are evidenced. Issues arising in the implementation of autonomic managers taking care of multiple concerns and of coordination among hierarchies of such autonomic managers are discussed. Experimental results are presented that demonstrate the feasibility of the approach.

关键词： parallel programming Skeleton Clouds Environmental management Computer science Computer architecture programming profession Distributed computing Clustering algorithms Algorithm design and analysis

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High performance computing using ProActive environment and the asynchronous iteration model

High performance computing using ProActive environment and t...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Raphael Couturier David Laiymani Sebastien Miquee Laboratoire d'Informatique de Franche-Comté (LIFC) University of Franche-Comté Belfort France

This paper presents a new library for the ProActive environment, called AIL-PA (asynchronous iterative library for ProActive). This new library allows to execute programs for solving large scale problems on various architectures. Two models of algorithm can be used: the synchronous iteration model which is efficient on single clusters; the asynchronous iteration model which is more efficient on distributed clusters. Both approaches are tested on both architectures, using Kernel CG of the NAS parallel Benchmarks on the Grid'5000 platform. These tests also allow us to compare ProActive with AIL-PA and with the Jace programming environment. The results show that the asynchronous iteration model with AIL-PA is more efficient on distributed clusters than the synchronous iteration model. Moreover, these experiments also show that AIL-PA does not involve additional overhead to ProActive.

关键词： High performance computing Libraries Large-scale systems Computer architecture Clustering algorithms Iterative algorithms Kernel Character generation Benchmark testing programming environments

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Job Scheduling Techniques for Distributed Systems with Heterogeneous Processor Cardinality

Job Scheduling Techniques for Distributed Systems with Heter...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Hung-Jui Chang Jan-Jan Wu Pangfeng Liu Department of Computer Science and Information Engineering National Taiwan University of Science and Technology Taipei Taiwan Institute of Information Science Research Center for Information Technology Innovation Academia Sinica Nankang Taiwan Department of Computer Science and Information Engineering Graduate Institute of Networking and Multimedia National Taiwan University of Science and Technology Taipei Taiwan

This paper proposes scheduling algorithms for assigning jobs with different release time and execution time, to machines with heterogeneous processor cardinality. We show that this scheduling problem is NP-complete, and propose dynamic programming to find the optimal schedules. Since the dynamic programming is time-consuming we propose techniques that improve the efficiency of the dynamic programming. We also propose heuristic algorithms for this scheduling problem. Experimental results suggest that some of the heuristics not only compute the answer efficiently but also provide good solution.

关键词： Processor scheduling Optimal scheduling Scheduling algorithm Grid computing Dynamic programming Biomedical computing Delay Approximation algorithms Computer science Heuristic algorithms

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Adaptivity in Risk and Emergency Management Applications on Pervasive Grids

Adaptivity in Risk and Emergency Management Applications on ...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Carlo Bertolli Gabriele Mencagli Marco Vanneschi Department of Computer Science University of Pisa Pisa Italy

Pervasive grid computing platforms are composed of a variety of fixed and mobile nodes, interconnected through multiple wireless and wired network technologies. Pervasive grid Applications must adapt themselves to the state of their surrounding environment which includes environmental data (e.g. collected from sensors) and the state of the used resources (e.g. network or node states). Adaptation is especially important if we consider complex high-performance pervasive grid applications, such as intelligent transportation and emergency management. In this paper we investigate how to define adaptivity for complex pervasive grid applications by providing multiple versions of application parallel modules. The versions are defined by exploiting different sequential algorithms and parallelization techniques. We introduce performance analysis tools for versions, which allow us to define specific selection policies of the best version to be executed, depending on the context. We show how each version is best suited to be executed on two application scenarios, also by means of experiments. To synthesize the contributions of this paper we introduce the ASSISTANT programming model, for adaptive pervasive grid applications.

关键词： Disaster management Risk management Grid computing Pervasive computing Floods Mobile computing Performance analysis parallel programming Application software Intelligent sensors

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MPIXternal: A library for a portable adjustment of parallel MPI applications to heterogeneous environments

MPIXternal: A library for a portable adjustment of parallel ...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Carsten Clauss Stefan Lankes Thomas Bemmerl Chair for Operation Systems RWTH Aachen University Aachen Germany

Nowadays, common systems in the area of high performance computing exhibit highly hierarchical architectures. As a result, achieving satisfactory application performance demands an adaptation of the respective parallel algorithm to such systems. This, in turn, requires knowledge about the actual hardware structure even at the application level. However, the prevalent Message Passing Interface (MPI) standard (at least in its current version 2.1) intentionally hides heterogeneity from the application programmer in order to assure portability. In this paper, we introduce the MPIXternal library which tries to circumvent this obvious semantic gap within the current MPI standard. For this purpose, the library offers the programmer additional features that should help to adapt applications to today's hierarchical systems in a convenient and portable way.

关键词： Libraries programming profession Hardware parallel algorithms Topology Computer architecture Hierarchical systems Communication standards Operating systems High performance computing

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dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core

dIP: A Non-intrusive Debugging IP for Dynamic Data Race Dete...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Chi-Neng Wen Shu-Hsuan Chou Tien-Fu Chen National Chung Cheng University Chiayi Taiwan

Traditional debug facilities are limited in providing debugging requirements for multicore parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. This work presents a fast and feasible hardware-assistant solution for many-core non-intrusive debugging. The key idea is to keep tracks of data accesses of shared memory areas and their lock synchronization activities by proposed data structures in proposed debugging IP (dIP). A page-based shared variable cache is provided to keep shared variables as long as possible, and an inexpensive pluggable off-chip RAM can eliminate the false-positive rate efficiently. To decrease the debugging traffic block, this work provides a thread library to specify shared memory/lock events and transmit those events to the dIP by a small proper hardware co-processor (eXtend dIP) of each core. Our experimental result shows the debugging traffic block (worse-case) by increasing cores, and adding tolerance buffers in XdIP can efficiently ease off. Moreover, the real workloads (SPLASH-2, MPEG-4, and H.264) are executed by the dIP non-instructive race-detection with only 4.7%~12.2% slow down in average. Finally, the hardware cost of dIP is also low when the growing of many-core.

关键词： Random access memory Hardware Multicore processing parallel programming Computer bugs Software debugging Data structures Read-write memory Yarn Libraries

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