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Design and Implementation of Music Information Retrieval and Gathering Engine (MIRAGE)

Design and Implementation of Music Information Retrieval and...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Jenq-Shiou Leu Chieh Changfan Kuan-Wu Su Chi-Feng Chen National Taiwan University of Science and Technology Taipei Taiwan Cadence Design Systems San Jose USA

Query by Singing/Humming (QBSH) is a most natural way for music recognition. A QBSH system can help find songs by matching a part of melody users sing or hum. Many Music Information Retrieval (MIR) techniques have been used to carry out the QBSH goal. In the past, little studies had ever been revealed about how to design and implement a simple QBSH system. In this article, we combine Short-Time-Fourier-Transform, Fourier Transform and Spectrum Analysis techniques at the client end, and Dynamic Time Warping (DTW) and dynamic programming techniques at the server end to implement Music Information Retrieval And Gathering Engine (MIRAGE), which can take input queries issued by users from web-based client-ends toward MIRAGE deployed at the server-end. MIRAGE can identify melody when a user only knows the rhythm of a song without any other information.

关键词： Music information retrieval Rhythm Dynamic programming Search engines Algorithm design and analysis Information analysis Data mining Internet Web server Fourier transforms

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Spatial Context-Awareness in Vehicular Ad Hoc Networks

Spatial Context-Awareness in Vehicular Ad Hoc Networks

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Attila Török Péter Laborczi Balázs Mezny Bay Zoltán Foundation for Applied Research Budapest Hungary

Distributed traffic information systems apply inter-vehicular ad hoc communication to disseminate road traffic information. The high amount of traffic information carried and flooded along the road network leads to superfluous forwarding, which is usually reduced by using rate- or spatial- adaptivity in the dissemination mechanisms. However, in certain cases due to the lack of context-aware information, the current protocols employing distributed spatial adaptivity will fail to achieve the desired performance. Therefore, an off-line heuristic algorithm (SPACE) was proposed to calculate on a digital map the Domain of Interest (DoI) of traffic jams. Based on this information, the dissemination protocol will be able to reduce more efficiently the superfluous forwarding. This paper takes a further step by proposing an Integer Linear programming (ILP) formulation for DoI optimizations, and analytically investigating the effect of spatial context-awareness on traffic information dissemination. The behavior of such a dissemination protocol is also explored through extensive simulations. Important characteristics on spatial adaptivity regarding the information dissemination strategies are concluded from the analytical and simulation results.

关键词： Ad hoc networks Telecommunication traffic Protocols Context Roads Information analysis Information systems Heuristic algorithms Integer linear programming Traffic control

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Linear optimization on modern GPUs

Linear optimization on modern GPUs

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Daniele G. Spampinato Anne C. Elster Department of Computer and Information Science Norwegian University of Science and Technology Trondheim Norway Norges teknisk-naturvitenskapelige universitet Trondheim NO

Optimization algorithms are becoming increasingly more important in many areas, such as finance and engineering. Typically, real problems involve several hundreds of variables, and are subject to as many constraints. Several methods have been developed trying to reduce the theoretical time complexity. Nevertheless, when problems exceed reasonable sizes they end up being very computationally intensive. Heterogeneous systems composed by coupling commodity CPUs and GPUs are becoming relatively cheap, highly performing systems. Recent developments of GPGPU technologies give even more powerful control over them. In this paper, we show how we use a revised simplex algorithm for solving linear programming problems originally described by Dantzig for both our CPU and GPU implementations. Previously, this approach has showed not to scale beyond around 200 variables. However, by taking advantage of modern libraries such as ATLAS for matrix-matrix multiplication, and the NVIDIA CUDA programming library on recent GPUs, we show that we can scale to problem sizes up to at least 2000 variables in our experiments for both architectures. On the GPU, we also achieve an appreciable precision on large problems with thousands of variables and constraints while achieving between 2X and 2.5X speed-ups over the serial ATLAS-based CPU version. With further tuning of both the algorithm and its implementations, even better results should be achievable for both the CPU and GPU versions.

关键词： Linear programming Computer graphics Hardware Finance Libraries Optimization methods Design automation Information science Power engineering computing High performance computing

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Irregular Grid Raycasting Implementation on the Cell Broadband Engine

Irregular Grid Raycasting Implementation on the Cell Broadba...

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international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Guilherme Cox Andre Maximo Cristiana Bentes Ricardo Farias Department of System Engineering State University of Rio De janeiro Rio de Janeiro Rio de Janeiro Brazil Centro de Tecnologia Federal University of Rio de Janeiro Rio de Janeiro Rio de Janeiro Brazil

Direct volume rendering has become a popular technique for visualizing volumetric data from sources such as scientific simulations, analytic functions, medical scanners, among others. Volume rendering algorithms, such as raycasting, can produce high-quality images, however, the use of raycasting has been limited due to its high demands on computational power and memory bandwidth. In this paper, we propose a new implementation of the raycasting algorithm that takes advantage of the highly parallel architecture of the Cell Broadband Engine processor, with 9 heterogeneous cores, in order to allow efficient raycasting of irregular datasets. All the computational power of the Cell BE processor, though, comes at the cost of a different programming model. Applications need to be rewritten, which requires using multithreading and vectorized code. In our approach, we tackle this problem by distributing ray computations using the visible faces, and vectorizing the lighting integral operations inside each core. Our experimental results show that we can obtain good speedups reducing the overall rendering time significantly.

关键词： Engines Rendering (computer graphics) Data visualization Computational modeling Analytical models Medical simulation Biomedical imaging Bandwidth parallel architectures Costs

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parallelizing Optimal Multiple Sequence Alignment by Dynamic programming

Parallelizing Optimal Multiple Sequence Alignment by Dynamic...

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IEEE international symposium on parallel and Distributed Processing with Applications

作者： Helal, Manal El-Gindy, Hossam Mullin, Lenore Gaeta, Bruno Univ New S Wales Sch Engn & Comp Sci Fac Engn Sydney NSW Australia Natl Sci Fdn Washington DC USA

ISBN: (纸本)9780769534718

Optimal multiple sequence alignment by dynamic programming, like many highly dimensional scientific computing problems, has failed to benefit from the improvements in computing performance brought about by multi-processor systems, due to the lack of suitable scheme to manage partitioning and dependencies. A scheme for parallel implementation of the dynamic programming multiple sequence alignment is presented, based on a peer to peer design and a multidimensional array indexing method. This design results in up to 5-fold improvement compared to a previously described master/slave design, and scales favourably with the number of processors used. This study demonstrates an approach for parallelising multi-dimensional dynamic programming and similar algorithms utilizing multi-processor architectures.

关键词： Sequence Alignment dynamic programming Multiprocessor computational performance PROCESSOR Processor architectures

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Task parallelism for object oriented programs

Task parallelism for object oriented programs

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9th international symposium on parallel architectures, algorithms and Networks, I-SPAN 2008

作者： Giacaman, Nasser Sinnen, Oliver Department of Electrical and Computer Engineering University of Auckland New Zealand

ISBN: (纸本)9780769531250

parallel computing is notoriously challenging due to the difficulty in developing correct and efficient programs. With the arrival of multi-core processors for desktop systems, desktop applications must now be parallelised. However achieving task parallelism for such object-oriented programs has traditionally been, and still remains, difficult. This paper presents a powerful task concept for parallel object-oriented programming and presents the results from a source-to-source compiler and runtime system. With the addition of a single keyword, the sequential code does not require restructuring and asynchronous task management is performed on behalf of the programmer;the parallel code required to realise task parallelism looks very much like the sequential counterpart. An intuitive solution is provided to handle task dependencies as well as integrating different task concepts into one model. © 2008 Crown Copyright.

关键词： Object oriented programming

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parallel execution of multi-set constraint rewrite rules 08

Parallel execution of multi-set constraint rewrite rules

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PPDP 2008: 10th international ACM SIGPLAN symposium on Principles and Practice of Declarative programming

作者： Sulzmann, Martin Lam, Edmund S. L. Programming Logics and Semantics Group IT University of Copenhagen Rued Langgaards Vej 7 2300 Copenhagen S Denmark School of Computing National University of Singapore S16 Level 5 3 Science Drive 2 Singapore 117543 Singapore

ISBN: (纸本)9781605581170

Multi-set constraint rewriting allows for a highly parallel computational model and has been used in a multitude of application domains such as constraint solving, agent specification etc. Rewriting steps can be applied simultaneously as long as they do not interfere with each other. We wish that the underlying constraint rewrite implementation executes rewrite steps in parallel on increasingly popular becoming multi-core architectures. We design and implement efficient algorithms which allow for the parallel execution of multi-set constraint rewrite rules. Our experiments show that we obtain some significant speed-ups on multi-core architectures. Copyright © 2008 ACM.

关键词： Computer architecture

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On the Performance of parallel Neural Network Implementations on Distributed Memory architectures 08

On the Performance of Parallel Neural Network Implementation...

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8th IEEE international symposium on Cluster Computing and the Grid

作者： Ganeshamoorthy, K. Ranasinghe, D. N. Univ Colombo Sch Comp Dept Computat & Intelligent Syst Colombo 07 Sri Lanka

ISBN: (纸本)9781424442379

In this paper, we study the impact of multi processor memory systems in particular, the distributed memory (I)M) and virtual shared memory (VSM), on the implementation of parallel backpropagation neural network algorithms. In the first instance, neural network is partitioned into sub neural networks by applying a hybrid partitioning scheme. In the second, each partitioned network is evaluated with matrix multiplication. Three different sizes of neural networks are used and exchange rate prediction used as a reference problem. parallel implementations for each of the distributed memory and virtual shared memory scenarios is obtained. These algorithms are implemented on a high performance cluster, "Monolith" consisting of over 396 nodes. programming is realized using Message Passing Interface (MPI) library and C-Linda. The partitioned, matrix multiplication has the fastest execution time, and DM/MPI implementation is always faster than the VSM/Linda equivalent. However in VSM/Linda it is possible to allow the parallel neural network to choose the optimum number of processors dynamically.

关键词： VSM DM Hybrid partition parallel neural network

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Hardware implementation of P systems using microcontrollers. An operating environment for implementing a partially parallel distributed architecture

Hardware implementation of P systems using microcontrollers....

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2008 10th international symposium on Symbolic and Numeric algorithms for Scientific Computing, SYNASC 2008

作者： Canaval, Sandra María Gómez Rodríguez, Abraham Gutiérrez Villaverde, Santiago Alonso Natural Computing Group Universidad Politécnica de Madrid Madrid Spain

ISBN: (纸本)9780769535234

Nowadays, important efforts in the research of the Transition P Systems have been focused on the simulation/ implementation of the massively parallel character of the model. The distributed implementation of P Systems has met with the communications bottleneck problem. In this sense, there are several research works on analysis for distributed architectures that are technology independent and avoiding communication collisions. Recent works present analysis on the suitability for implementing theses architectures using an universal membrane hardware/software component based on microcontrollers. These implementations are directly programming on hardware components and the resulting data is analyzed by means of a specific program which translates the execution bit code into intelligible data for researchers. The aim of this work is to present an operating environment to automate manual tasks performed during the loading, execution and interpretation of P System into distributed architectures based on microcontrollers as well as the interpretation from inner binary data representation inside of microcontrollers. © 2008 IEEE.

关键词： Microcontrollers

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Embedding smart buffers for window operations in a stream-oriented C-to-VHDL compiler

Embedding smart buffers for window operations in a stream-or...

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4th IEEE international symposium on Electronic Design, Test and Applications

作者： Diet, Fabian D'Hollander, Erik H. Beyls, Kristof Devos, Harald Univ Ghent ELIS Dept Parallel Informat Syst B-9000 Ghent Belgium

ISBN: (纸本)9780769531106

Important classes of algorithms which can benefit from the advantages of C-to-VHDL compiling are window operations. These execute a number of instructions on a large amount of array data. Since arrays are usually translated into FPGA block memory structures, it is important to minimize the required number of block memory accesses. Recently, a smart buffer has been introduced, in which a number of past and present array elements can be temporarily stored to be reused over a number of different loop nest iterations. In this paper, the smart buffer approach is analysed for use in the stream-oriented Impulse-C compiler. Experimental automatic generation of VHDL code for this buffer is described. The smart buffer is then linked with the VHDL code generated by the Impulse-C compiler to obtain data efficient designs.

关键词： C (programming language)

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