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Performance comparison of parallel programming environments for implementing AIAC algorithms

JOURNAL OF SUPERCOMPUTING 2006年第3期35卷 227-244页

作者： Bahi, JM Contassot-Vivier, S Couturier, R IUT Belfort Montbeliard LIFC F-90016 Belfort France

AIAC algorithms (Asynchronous Iterations Asynchronous Communications) are a particular class of parallel iterative algorithms. Their asynchronous nature makes them more efficient than their synchronous counterparts in numerous cases as has already been shown in previous works. The first goal of this article is to compare several parallel programming environments in order to see if there is one of them which is best suited to efficiently implement AIAC algorithms. The main criterion for this comparison consists in the performances achieved in a global context of grid computing for two classical scientific problems. Nevertheless, we also take into account two secondary criteria which are the ease of programming and the ease of deployment. The second goal of this study is to extract from this comparison the important features that a parallel programming environment must have in order to be suited for the implementation of AIAC algorithms.

关键词： parallel programming (Computer science) parallel computers COMPUTER algorithms ASYNCHRONOUS transfer mode parallel processing (Electronic computers) COMPUTER systems COMPUTER network architectures COMPUTER science COMPUTER programming

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Integer linear programming method for spatial temporal mapping of the viterbi decoder

Integer linear programming method for spatial temporal mappi...

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IEEE international symposium on Circuits and Systems

作者： Appaya, Devaraj S. Avessta, Nastooh Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9780780393899

Array processors are gaining importance as fabrication technology scales down. Thus a simple and systematic method to implement algorithms in array architectures is desirable. In this paper a general Integer Linear Program (ILP) is formulated to minimize computation time and interconnection length. The ILP is solved with various constraints on the parallel computation time and interconnect space. Different cost functions as desired by the designer can be added to the optimization process. Viterbi decoder is considered as a case study. Optimum array architecture is obtained using the proposed ILP.

关键词： Integer programming

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Bulk synchronous parallel ML:: Semantics and implementation of the parallel juxtaposition 1

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international Computer Science symposium in Russia (CSR 2006)

作者： Loulergue, F. Benheddi, R. Gava, F. Louis-Regis, D. Univ Orleans Fondamentale Orleans Lab Informat F-45067 Orleans France Univ Paris 12 Lab Algorithms Complex & Log F-94010 Creteil France

ISBN: (数字)9783540341680

ISBN: (纸本)3540341668

The design of parallel programs and parallel programming languages is a trade-off. On one hand the programs should be efficient. But the efficiency should not come at the price of non portability and unpredictability of performances. The portability of code is needed to allow code reuse on a wide variety of architectures and to allow the existence of legacy code. The predictability of performances is needed to guarantee that the efficiency will always be achieved, whatever is the used architecture.

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seventh international Conference on parallel and Distributed Computing, Applications and Technologies-Title

Seventh International Conference on Parallel and Distributed...

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IEEE international Conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

The following topics are dealt with: parallel computing; distributed computing; interconnection networks; communication and telecommunication; image processing and computer graphics; access control and authorization; wireless networks and mobile computing; database applications and data mining; parallelizing compilers; parallel/distributed architectures; intelligent computing and neural networks; Internet computing; network routing and communication algorithms; Web technologies; ubiquitous computing systems; task mapping and job scheduling; security protocols; computer networks; formal methods and programming languages; intrusion detection and survivability; grid computing systems; applied cryptography; P2P and ad hoc networks; and reliability and fault-tolerance

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GPU-ABiSort: optimal parallel sorting on stream architectures 06

GPU-ABiSort: optimal parallel sorting on stream architecture...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： A. Greb G. Zachmann Institute of Computer Science II Rhein Friedr.-Wilh.-Universität Bonn Bonn Germany Institute of Computer Science Clausthal University of Technology Clausthal Germany

ISBN: (纸本)9781424400546

In this paper, we present a novel approach for parallel sorting on stream processing architectures. It is based on adaptive bitonic sorting. For sorting n values utilizing p stream processor units, this approach achieves the optimal time complexity O((n log n)/p). While this makes our approach competitive with common sequential sorting algorithms not only from a theoretical viewpoint, it is also very fast from a practical viewpoint. This is achieved by using efficient linear stream memory accesses (and by combining the optimal time approach with algorithms optimized for small input sequences). We present an implementation on modern programmable graphics hardware (GPUs). On GPUs, our optimal parallel sorting approach has shown to be remarkably faster than sequential sorting on the CPU, and it is also faster than previous non-optimal sorting approaches on the GPU for sufficiently large input sequences. Because of the excellent scalability of our algorithm with the number of stream processor units p (up to n/log/sup 2/ n or even n/log n units, depending on the stream architecture), our approach profits heavily from the trend of increasing number of fragment processor units on GPUs, so that we can expect further speed improvement with upcoming GPU generations.

关键词： Sorting Hardware Computer architecture Computer science Graphics Scalability parallel architectures parallel algorithms parallel programming programming profession

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Realizing Multioperations for Step Cached MP-SOCs

Realizing Multioperations for Step Cached MP-SOCs

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IEEE international symposium on System-on-Chip

作者： Martti Forsell Platform Architectures Team Oulu Finland

Recent advances in shared memory multiprocessor system-on-chip (MP-SOC) architectures include using special step caches to efficiently implement concurrent read concurrent write memory access. Unfortunately the existing step cache techniques do not support multioperations that can be used to speed up execution of a number of parallel algorithms by a logarithmic factor. This paper proposed an architectural technique for implementing multioperations on step cached MP-SOCs even if the associativity of caches is limited. The technique is based on simple active memory units, faster memory modules, and small processor-level memory blocks called scratchpads. The performance and area requirements of the proposed technique were evaluated on the parametrical MP-SOC framework. According to the evaluation the technique implements multioperations efficiently and provides a speed-up of 4.8 - 7.2 with respect baseline step cached systems and a speed-up of 3.7- 5.0 with respect to existing non-step cached systems with only a minor silicon are overhead

关键词： Read-write memory Yarn parallel algorithms Memory architecture Multiprocessing systems Silicon Message passing System-on-a-chip programming profession Hardware

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LogfP - a model for small messages in InfiniBand 06

LogfP - a model for small messages in InfiniBand

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international symposium on parallel and Distributed Processing (IPDPS)

作者： T. Hoefler T. Mehlan F. Mietke W. Rehm Department of Computer Science Chemnitz University of Technology Chemnitz Germany

ISBN: (纸本)9781424400546

Accurate models of parallel computation are often crucial to optimize parallel algorithms for their running time. In general the easier the model's use and the smaller the number of parameters and interdependencies among them, the more inaccuracies are introduced by simplification. On the other hand a too complex model is unusable. We show that it is possible to derive a relatively accurate and easy model for small message performance over the InfiniBand network. This model allows the developer to gain knowledge about the inherent parallelism of a specific InfiniBand hardware and encourages him to use this parallelism efficiently. Several well known models hide this feature and some of them even penalize the use of parallelism because the model designers were not aware of new emerging architectures like InfiniBand

关键词： parallel processing Algorithm design and analysis programming profession Concurrent computing parallel algorithms Hardware Computer architecture Delay Computer networks Bandwidth

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A multiprocessor architecture for the massively parallel model GCA 06

A multiprocessor architecture for the massively parallel mod...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： W. Heenes R. Hoffmann J. Jendrsczok TU Darmstadt FB Informatik FG Rechnerarchitektur Darmstadt Germany

ISBN: (纸本)9781424400546

The GCA (global cellular automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA model. In differentiation to the CA model the neighbors are not fixed and local, they are variable and global. The GCA model is applicable to a wide range of parallel algorithms. In this paper, a multiprocessor architecture for the massively parallel GCA model is presented. In contrast to a special purpose implementation of a GCA algorithm the multiprocessor system allows the implementation in a flexible way through programming. The architecture mainly consists of a number of cell processors and a network. The cell processors are dedicated RISC processors, the network is a crossbar implemented with multiplexers. Only read-accesses through the network are necessary in the GCA model leading to a simplified structure. A system with 32 processors was implemented as a prototype on a FPGA. The analysis and implementation results have shown that the performance of the system scales very well with the number of processors

关键词： Computer architecture Hardware Field programmable gate arrays parallel architectures parallel algorithms Multiprocessing systems Reduced instruction set computing Multiplexing Prototypes Performance analysis

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Integer Linear programming Method for Spatial Temporal Mapping of the Viterbi Decoder

Integer Linear Programming Method for Spatial Temporal Mappi...

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Proceedings of 2006 IEEE international symposium on Circuits and Systems,Volume 4

作者： Appaya Devaraj, S. Nastooh Avessta Department of Information Technology University of Turku Turku Finland

关键词： Integer linear programming Viterbi algorithm Decoding Cost function Fabrication Convolutional codes Design optimization Systolic arrays Information technology Computer architecture

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Theory and practice of programming applied to membrane systems (Invited talk)

Theory and practice of programming applied to membrane syste...

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7th international symposium on Symbolic and Numeric algorithms for Scientific Computing

作者： Ciobanu, G Res Inst eAustria Timisoara Romania

ISBN: (纸本)0769524532

Following the knowledge provided by the theory of programming, we present an abstract syntax of the membrane systems, and their semantics. We define an appropriate notion of configurations, and sets of inference rules corresponding to the three stages of an evolution step in membrane systems. A notion of bisimulation is defined;bisimulation relations allow to compare the evolution behaviour of two membrane systems. On the other hand, the practice of programming related to membrane systems is given by the presentation of some sequential and parallel software simulators, emphasizing their specific features.

关键词： Computer programming

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