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Nonlinear optimization and parallel computing

Nonlinear optimization and parallel computing

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international Conference on parallel Computing in Numerical Optimization (ParCo 2001)

作者： Migdalas, A Toraldo, G Kumar, V Tech Univ Crete DSS Lab Khania 73100 Greece Univ Naples Federico II Dipartimento Ingn Agr & Agron Territorio I-80055 Portici Italy CNR ICAR Sez Napoli I-80100 Naples Italy Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA

The new computational technologies are having a very strong influence on numerical optimization, in several different ways. Many researchers have been stimulated by the need to either conform the existing numerical techniques to the new parallel architectures or to devise completely new parallel solution approaches. A mini-symposium on parallel Computing in Nonlinear Optimization was held in Naples, Italy, September 2001, during the international Conference ParCo2001, in order to bring together researchers active in this field and to discuss and share their findings. Some of the papers presented during the mini-symposium, as well as additional contributions from other researchers are collected in this special issue. Clearly, two different trends, well representative for most of the current research activities, can be identified. Firstly, there is an attempt to encapsulate parallel/linear algebra software and algorithms into optimization codes, particularly codes implementing interior point strategies for which the linear algebra issues are very critical, and secondly, there is an effort to devise new parallel solution strategies in global optimization, either for specific or general purpose problems, motivated by the large size and the combinatorial nature of them. In the present paper we review the literature on these trends and classify the contributed papers within this framework. (C) 2003 Elsevier Science B.V. All rights reserved.

关键词： parallel computing quadratic programming interior point methods global optimization heuristics

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Proceedings international parallel and Distributed Processing symposium

Proceedings International Parallel and Distributed Processin...

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international symposium on parallel and Distributed Processing (IPDPS)

The following topics are dealt with: Grid and distributed computing; scheduling task systems; shared-memory multiprocessors; imaging and visualization; testing and debugging; performance analysis and real-time systems; scheduling for heterogeneous resources; networking; peer-to-peer and mobile computing; compiler technology and run-time systems; load balancing; network routing; parallel programming models; parallel algorithms; scheduling and storage; parallel and distributed performance; software for high performance clusters; decentralized algorithms; multithreading and VLIW; parallel and distributed real-time systems; high-level parallel programming models and supportive environments; Java for parallel and distributed computing; nature inspired distributed computing; high performance computational biology; advances in parallel and distributed computational models; reconfigurable architectures; communication architecture for clusters; next generation systems; fault-tolerant parallel and distributed systems; wireless, mobile and ad hoc networks; parallel and distributed image processing, video processing, and multimedia; formal methods for parallel programming; Internet computing and e-commerce; parallel and distributed scientific and engineering computing with applications; massively parallel processing; performance modeling, evaluation, and optimization of parallel and distributed systems; and parallel and distributed systems: testing and debugging.

关键词： Processor scheduling Shared memory systems Software debugging Software testing Real time systems Program compilers Resource management parallel programming parallel algorithms Memory management parallel architectures Biomedical computing Reconfigurable architectures Computer fault tolerance Video signal processing Image processing Software requirements and specifications Multimedia computing Internet

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Semi-structured portable library for multiprocessor servers

Semi-structured portable library for multiprocessor servers

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international symposium on parallel and Distributed Processing (IPDPS)

作者： G. Tsilikas M. Fleury Electronic Systems Engineering Department Multimedia Architectures Laboratory University of Essex Colchester Essex UK

The MiPPS library supports a hybrid model of parallel programming. The library is targeted at commodity multiprocessors, with support for clusters. The implementation of the concurrency routines reveals discrepancies between popular operating systems. Tests on suitable applications also reveal similar discrepancies in performance across different multiprocessors. The MiPPS library has also been the basis of a parallelization of the Active Chart Parsing algorithm for speech understanding.

关键词： Software libraries Hidden Markov models Object oriented modeling parallel programming Operating systems Message passing Data structures Application software Software algorithms Speech

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A distributed hierarchical programming model for heterogeneous cluster of SMPs

A distributed hierarchical programming model for heterogeneo...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： T. Rauber G. Runger S. Trautmann Fakultät für Mathematik und Physik Universität Bayreuth Bayreuth Germany Fakultät für Informatik Technische Universität Chemnitz-Zwickau Chemnitz Germany

Cluster systems are getting increasingly popular since they provide large computational power at a reasonable price. The cluster nodes are often SMP with a small number of processors that can access a shared address space. The nodes are connected by a network like Myrinet or SCI, so the global address space is distributed. In this paper, we present a new programming model for such clusters of SMP. The model allows the programmer to adapt his program to the two-level structure of the address space by providing a micro-level and a macro-level. The micro-level allows a thread formulation of multiprocessor tasks that are executed within a node of the cluster system. The macro-level allows the hierarchical structuring of multiprocessor-tasks according to the structure of the algorithm using message passing for data-exchange. We demonstrate the usefulness of the approach by runtime tests on several cluster systems with different node architectures and different interconnection networks.

关键词： Switched-mode power supply Libraries Runtime parallel machines Yarn Multiprocessor interconnection networks Power system modeling programming profession Clustering algorithms Message passing

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DSP performance evaluation for motion estimation

DSP performance evaluation for motion estimation

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international symposium on Signal Processing and Its Applications (ISSPA)

作者： L. Louro P. Santos N. Rodrigues V. Silva S. Faria Instituto de Telecomunicações DEEC Pólo II da Universidade de Coimbra Coimbra Portugal Escola Superior de Tecnologia e Gestão Institnto Politécnico de Leíria Leiria Portugal

In this paper, we analyze the performance of the floating point digital signal processor (DSP) TMS320C6711 for an implementation of video coding motion. Two relevant motion estimation techniques were implemented: BMA (block matching algorithm) and BMGT (block matching using geometric transforms). These have been combined with fast block matching algorithms to speed up the process. In order to increase the DSP performance, we have optimized some programming mechanisms like: the level of code parallelism, hand designed assembly code and an efficient usage of internal memory as cache. This implementation has shown that real-time motion estimation of BMA type, can be implemented in this DSP. However. BMGT type motion estimation cannot be done by one DSP alone in-real time applications, due to its high computational complexity.

关键词： Digital signal processing Motion estimation Signal processing algorithms Signal analysis Performance analysis Digital signal processors Video coding Motion analysis Design optimization parallel programming

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Performance evaluation of two emerging media processors: VIRAM and Imagine

Performance evaluation of two emerging media processors: VIR...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Chatterji M. Narayanan J. Duell L. Oliker Computer Science Division University of California Berkeley CA USA Computer Science Research Division Lawrence Berkeley National Laboratory Berkeley CA USA

This work presets two emerging media microprocessors, VIRAM and Imagine, and compares the implementation strategies and performance results of these unique architectures. VIRAM is a complete system on a chip which uses PIM technology to combine vector processing with embedded DRAM. Imagine is a programmable streaming architecture with a specialized memory hierarchy designed for computationally intensive data-parallel codes. First, we preset a simple and effective approach for understanding and optimizing vector/stream applications. Performance results are then presented from a number of multimedia benchmarks and a computationally intensive scientific kernel. We explore the complex interactions between programming paradigms, the architectural support at the ISA level and the underlying microarchitecture of these two systems. Our long term goal is to evaluate leading media microprocessors as possible building blocks for future high performance systems.

关键词： Streaming media Computer architecture Computer science Instruction sets Microarchitecture Signal processing algorithms Kernel parallel processing Delay Multimedia systems

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VLIW operation refinement for reducing energy consumption

VLIW operation refinement for reducing energy consumption

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IEEE international symposium on System-on-Chip

作者： U. Hirnschrott A. Krall CD-Lab Compilation Techniques for Embedded Processors Technische Univ. Wien Austria CD-Lab Compilation Techniques for Embedded Processors Technische Universität Wien Wien Austria

The demand for mobile computer power has exploded in the recent years. Variable length VLIW processors offer the necessary performance at low power. Software optimizations are necessary to further decrease the energy consumption. In this article we present a compiler optimization which reduces the dynamic power dissipation resulting from the switching activities during instruction fetch. Energy consumption can be reduced by minimizing the Hamming distance between successively fetched instruction words. Using a dynamic programming approach we first compute a set of optimal instruction arrangements of the execution bundles in a basic block. These sets are used in an enumerative optimal algorithm and a genetic evolution, in order to minimize an objective function for the Hamming distance. We evaluated our algorithms on different variable length VLIW architectures with 3 to 6 parallel functional units. On a large set of DSP benchmark programs the Hamming distance can be reduced by about 10% on average. Maximum reductions range up to 30%.

关键词： VLIW Energy consumption Hamming distance Mobile computing Optimizing compilers Power dissipation Dynamic programming Computer aided instruction Genetics Computer architecture

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The Pensieve Project: A compiler infrastructure for memory models

The Pensieve Project: A compiler infrastructure for memory m...

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6th international symposium on parallel architectures, algorithms and Networks (I-SPAN 02)

作者： Wong, CL Sura, Z Fang, X Midkiff, SP Lee, JJ Padua, D Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)0769515797

The design of memory consistency models for both hardware and soft-ware is a difficult task. It is particularly difficult for a programming language because the target audience is much wider than the target audience for a machine language, making usability a more important criteria. Adding to this problem is the fact that the programming language community has little experience designing programming language consistency models, and therefore each new attempt is very much a voyage into uncharted territory. A concrete example of the difficulties of the task is the current Java Memory Model. Although designed to be easy to use by Java programmers, it is poorly understood and at least one common idiom (the "double check idiom") to exploit the model is unsafe. In this paper we describe the design of an optimizing Java compiler that will accept, as either input or as an interface implementation, a consistency model for the code to be compiled The compiler will use escape analysis, Shasha and Snir's delay set analysis, and our CSSA program representation to normalize the effects of different consistency models on optimizations and analysis. When completed, the compiler will serve as a testbed to prototype new memory models, and to measure the differences of different memory models on program performance.

关键词： Computer languages Concrete Delay effects Design optimization Hardware Java Optimizing compilers Program processors programming profession Usability

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A simple and efficient parallel disk mergesort

A simple and efficient parallel disk mergesort

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11th Annual ACM symposium on parallel algorithms and architectures

作者： Barve, RD Vitter, JS Winphoria Networks Andheri 400093 Mumbai India Duke Univ Dept Comp Sci Ctr Geometr & Biol Comp Durham NC 27708 USA

External sorting-the process of sorting a file that is too large to fit into the computer's internal memory and must be stored externally on disks-is a fundamental subroutine in database systems [G], [IBM]. Of prime importance are techniques that use multiple disks in parallel in order to speed up the performance of external sorting. The simple randomized merging (SRM) mergesort algorithm proposed by Barve et al. [BGV] is the first parallel disk sorting algorithm that requires a provably optimal number of passes and that is fast in practice. Knuth [K, Section 5.4.9] recently identified SRM (which he calls "randomized striping") as the method of choice for sorting with parallel disks. In this paper we present an efficient implementation of SRM, based upon novel and elegant data structures. We give a new implementation for SRM's lookahead forecasting technique for parallel prefetching and its forecast and flush technique for buffer management. Our techniques amount to a significant improvement in the way SRM carries out the parallel, independent disk accesses necessary to read blocks of input runs efficiently during external merging. Our implementation is based on synchronous parallel I/O primitives provided by the TPIE programming environment [TPI], whenever our program issues an I/O read (write) operation, one block of data is synchronously read from (written to) each disk in parallel. We compare the performance of SRM over a wide range of input sizes with that of disk-striped mergesort (DSM), which is widely used in practice. DSM consists of a standard mergesort in conjunction with striped I/O for parallel disk access. SRM merges together significantly more runs at a time compared with DSM, and thus it requires fewer merge passes. We demonstrate in practical scenarios that even though the streaming speeds for merging with DSM are a little higher than those for SRM (since DSM merges fewer runs at a time), sorting using SRM is often significantly faster than with DSM

关键词： Computation theory

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XtremWeb:: A generic Global Computing system

XtremWeb:: A generic Global Computing system

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1st IEEE/AMC international symposium on Cluster Computing and the Grid

作者： Fedak, G Germain, C Néri, V Cappello, F Univ Paris 11 Rech Informat Lab Orsay France

ISBN: (纸本)0769510116

Global Computing achieves high throughput computing by harvesting a very large number of unused computing resources connected to the Internet. This parallel computing model targets a parallel architecture defined by a very high number of nodes, poor communication performance and continuously varying resources. The unprecedented scale of the Global Computing architecture paradigm requires to revisit many, basic issues related to parallel architecture : programming models, performance models, and class of applications or algorithms suitable to this architecture, XtremWeb is an experimental Global Computing platform dedicated to provide a tool for such studies. This paper presents the design of XtremWeb. Two essential features of this design are multi-applications and high-performance. Accepting multiple applications allows institutions or enterprises to setup their own Global Computing applications or experiments. High-performance is ensured by scalability, fault tolerance, efficient scheduling and a large base of volunteer PCs. We also present an implementation of the first global application running on XtremWeb.

关键词： parallel architectures

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