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共 511 条记录，以下是371-380 订阅

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FEAS: A Faster Event-driven Accelerator Supporting Inhibitory Spiking Neural Network

FEAS: A Faster Event-driven Accelerator Supporting Inhibitor...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Songsong Li Lei Gong Teng Wang Chao Wang Xuehai Zhou University of Science and Technology of China Heifei China

ISBN: (纸本)9781665496407

In recent years, the spiking neural network (SNN) has gained widespread attention for its low latency and low power consumption characteristics. Customizing accelerators to exploit the parallelism in SNN fully has become a current research hotspot. Because the calculations between different time steps in SNN have dependencies, the existing accelerators update the neuron state strictly in time sequence, which results in the calculation of SNN even more than that of the artificial neural network (ANN). In addition, traditional event-driven SNN accelerators cannot support inhibitory SNN models, which severely limits their scope of application. Based on this observation, we combined the characteristics of the most commonly used neuron model and spike code to design an event-driven SNN accelerator (FEAS). FEAS realizes the acceleration for SNN (both the excitatory SNN and the inhibitory SNN) models through algorithm approximation and novel hardware modules. We use FEAS to accelerate a fully connected SNN model for classification on the MNIST dataset. The results show that compared with the state-of-the-art technology, our accelerator can increase the throughput by an order of magnitude with the model's accuracy as high as 97.54%.

关键词： Power demand Neurons Artificial neural networks programming parallel processing Approximation algorithms Throughput

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A Comparison of High-Level programming Choices for Incomplete Sparse Factorization Across Different architectures

A Comparison of High-Level Programming Choices for Incomplet...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Joshua Dennis Booth Kyungjoo Kim Sivasankaran Rajamanickam Center for Computing Research Sandia National Laboratories Albuquerque NM USA

ISBN: (纸本)9781509036837

All many-core systems require fine-grained shared memory parallelism, however the most efficient way to extract such parallelism is far from trivial. Fine-grained parallel algorithms face various performance trade-offs related to tasking, accesses to global data-structures, and use of shared cache. While programming models provide high level abstractions, such as data and task parallelism, algorithmic choices still remain open on how to best implement irregular algorithms, such as sparse factorizations, while taking into account the trade-offs mentioned above. In this paper, we compare these performance trade-offs for task and data parallelism on different hardware architectures such as Intel Sandy Bridge, Intel Xeon Phi, and IBM Power8. We do this by comparing the scaling of a new task-parallel incomplete sparse Cholesky factorization called Tacho and a new data-parallel incomplete sparse LU factorization called Basker. Both solvers utilize Kokkos programming model and were developed within the ShyLU package of Trilinos. Using these two codes we demonstrate how high-level programming changes affect performance and overhead costs on multiple multi/many-core systems. We find that Kokkos is able to provide comparable performance with both parallel_for and task/futures on traditional x86 multicores. However, the choice of which high-level abstraction to use on many-core systems depends on both the architectures and input matrices.

关键词： parallel processing Sparse matrices programming Multicore processing Program processors Hardware

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A Translation Framework for Virtual Execution Environment on CPU/GPU Architecture

A Translation Framework for Virtual Execution Environment on...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Guoxing Dong Kai Chen Erzhou Zhu Yichao Zhang Zhengwei Qi Haibing Guan School of Software Shanghai Jiaotong University Shanghai China School of Information Security Engineering Shanghai Jiaotong University Shanghai China Department of Computer Science and Engineering Shanghai Key Laboratory of Scalable Computing and Systems Shanghai Jiaotong University Shanghai China

GPUs are many-core processors with tremendous computational power. However, as automatic parallelization has not been realized yet, developing high-performance parallel code for GPUs is still very challenging. The paper presents a novel translation framework designed for virtual execution environment based on CPU/GPU architecture. It addresses two major challenges of taking advantage of general purpose computation on graphics processing units (GPGPU) to improve performance: no rewriting the existing source code and resolving binary compatibility issues between different GPUs. The translation framework uses semi-automatic parallelization technology to port existing code to explicitly parallel programming models. It not only offers a mapping strategy from X86 platform to CUDA programming model, but also synchronizes the execution between the CPU and the GPUs. The input to our translation framework is parallelizable part of the program within binary code. With an additional information related to the parallelizable part, the translation framework transforms the sequential code into PTX code and execute it on GPUs. Experimental results on several programs from CUDA SDK Code Samples and Parboil Benchmark Suite show that our translation framework could achieve very high performance, even up to several tens of times speedup over the X86 native version.

关键词： Graphics processing unit Registers Kernel Instruction sets Driver circuits programming Computer architecture

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Autonomic management of non-functional concerns in distributed & parallel application programming

Autonomic management of non-functional concerns in distribut...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Marco Aldinucci Marco Danelutto Peter Kilpatrick Department Computer Science University of Torino Torino Italy Department Computer Science University of Pisa Pisa Italy Department Computer Science Queen''s University Belfast Belfast UK

ISBN: (纸本)9781424437511

An approach to the management of non-functional concerns in massively parallel and/or distributed architectures that marries parallel programming patterns with autonomic computing is presented. The necessity and suitability of the adoption of autonomic techniques are evidenced. Issues arising in the implementation of autonomic managers taking care of multiple concerns and of coordination among hierarchies of such autonomic managers are discussed. Experimental results are presented that demonstrate the feasibility of the approach.

关键词： parallel programming Skeleton Clouds Environmental management Computer science Computer architecture programming profession Distributed computing Clustering algorithms Algorithm design and analysis

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An extensible framework for coherence in distributed shared data systems

An extensible framework for coherence in distributed shared ...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： H. Sandhu Department of Computer Science York University Canada

The choice of sharing model (objects vs. plain shared memory), memory consistency model and coherence protocol are all fundamental aspects of the design of distributed shared data systems. Unfortunately, no single sharing model, memory model or coherence protocol is suitable for all applications. In this paper, we describe the design of an extensible distributed shared data framework, called the Extensible Coherence Interface (ECI), that gives the application layer complete control over how data is shared, including whether to share data on a per-object basis or per-page, which memory model to use, and how coherence is enforced for a region of shared memory. The ECI implementation itself simply acts as a layer for transporting and dispatching distributed events among objects at the application layer.

关键词： Data systems Coherence Electrical capacitance tomography Protocols programming profession Computer science Random access memory Identity-based encryption Memory management

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CheR: Cheating resilience in the cloud via smart resource allocation

CheR: Cheating resilience in the cloud via smart resource al...

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6th international symposium on Foundations and Practice of Security, FPS 2013

作者： Roberto, Di Pietro Lombardi, Flavio Martinelli, Fabio Sgandurra, Daniele Department of Mathematics and Physics University Roma Tre Largo S. Leonardo Murialdo 00146 Rome Italy Institute for Informatics and Telematics National Research Council of Italy Pisa Italy

ISBN: (纸本)9783319053011

Cloud computing offers unprecedented ways to split and offload the workload of parallel algorithms to remote computing nodes. However, such remote parties can potentially misbehave, for instance by providing fake computation results in order to save resources. In turn, these erroneous partial results can affect the timeliness and correctness of the overall outcome of the algorithm. The widely successful cloud approach increases the economic feasibility of leveraging computational redundancy to enforce some degree of assurance about the results. However, naïve solutions that dumbly replicate the same computation over several sets of nodes are not cost-efficient. In this paper, we provide several contributions as for the distribution of workload over (heterogeneous) cloud nodes. In particular, we first formalize the problem of computing a parallel function over a set of nodes;later, we introduce CheR (for Cheating Resilience), a novel approach based upon modelling the assignment of input elements to cloud nodes as a linear integer programming problem aimed at minimizing cost while being resilient against misbehaving nodes. Further, we describe the CheR approach in different scenarios and highlight the novelty with respect to other state-of-the-art solutions. Finally, we present and discuss some experimental results showing the viability and quality of our proposal. © 2014 Springer international Publishing Switzerland.

关键词： Integer programming

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Efficient parallel mappings of a dynamic programming algorithm: a summary of results

Efficient parallel mappings of a dynamic programming algorit...

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international symposium on parallel Processing

作者： G. Karypis V. Kumar Department of Computer Science University of Minnesota Minneapolis MN USA

The authors are concerned with dynamic programming (DP) algorithms whose solution is given by a recurrence relation similar to that for the matrix parenthesization problem. Guibas, Kung and Thompson (1979), presented a systolic array algorithm for this problem that uses O(n/sup 2/) processing cells and solves the problem in O(n) time. The authors present three different mappings of this systolic algorithm on a mesh connected parallel computer. The first two mappings use commonly known techniques for mapping systolic arrays to mesh computers. Both of them are able to obtain only a fraction of maximum possible performance. The primary reason for the poor performance of these formulations is that different nodes at different levels in the multistage graph in the DP formulation require different amounts of computation. Any adaptation has to take this into consideration and evenly distribute the work among the processors. The third mapping balances the work load among processors and thus is capable of providing efficiency approximately equal to 1 (i.e., speedup approximately equal to the number of processors) for any number of processors and sufficiently large problem. They experimentally evaluate these mappings on a mesh embedded onto a 256 processor nCUBE/2.< >

关键词： Dynamic programming Heuristic algorithms Concurrent computing Systolic arrays Military computing Equations Computer science Problem-solving Industrial engineering Contracts

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Adapting a partitioning-based heuristic load-balancing algorithm to heterogeneous computing environments

Adapting a partitioning-based heuristic load-balancing algor...

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international symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： D. Petcu Computer Science Department Institute e-Austria TimiInstitute e-Austria Timişoara Western University of Timişoara Romania

A graph partitioning-based heuristic load-balancing algorithm known as the largest-task-first-with-minimum-finish-time-and-available-communication-costs from EVAH package by M.J. Djomehri, et. al. (2003) is modified in order to be dynamically adapted to heterogeneous computing environments like a grid. An example is given to show the improvement.

关键词： Heuristic algorithms Partitioning algorithms Load management Grid computing Packaging parallel processing Mathematical programming History Computational fluid dynamics Costs

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MCVAE: Multi-channel Variational Autoencoder for Anomaly Detection

MCVAE: Multi-channel Variational Autoencoder for Anomaly Det...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Wanzhen Zhang Liheng Xu Zhihui Yu Zikai Zhang Tonglai Liu Shuangyin Liu Engineering Trainning Center Guilin University of Aerospace Technology (College of Information Science and Technology Zhongkai University of Agriculture and Engineering) Guilin China College of Information Science and Technology Zhongkai University of Agriculture and Engineering Guangzhou China State Key Lab of Rail Traffic Control & Safety Beijing Jiaotong University Beijing China

ISBN: (纸本)9781665452199

Unsupervised anomaly detection is a very important problem due to its wide applications in many systems such as the network communication system, the Internet of Things, and the ICS system. Interpretable modeling of heterogeneous data channels is also essential in anomaly detection, due to the intrinsic multi-modality in multi-channel multi-dimension data. Some existing works use variational autoencoder (VAE) for anomaly detection with a single Gaussian distribution model. However, these VAE can not learn the complex distribution between features, and hence cannot make accurate detections. To tackle this challenge, in this paper, we propose a multi-channel VAE model to jointly account for latent relationships across multiple channels. Moreover, we explore the training loss function combining the reconstruction loss of each channel. We also explore the test loss combining the reconstruction probability and reconstruction ratio between global channel information and each channel information. The proposed detector reports an anomaly when the test loss is below a certain threshold. We conduct extensive simulations on a real world dataset and find that our proposed scheme outperforms the state-of-the-art anomaly detection schemes compared with existing methods.

关键词： Training Detectors programming Gaussian distribution Feature extraction parallel architectures Internet of Things

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Cache Optimization Method to Reduce Network Traffic in Communication Systems

Cache Optimization Method to Reduce Network Traffic in Commu...

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international symposium on parallel architectures, algorithms and programming (PAAP)

作者： Ruey-Shun Chen Yu-Xi Hu Xiaopeng Fan Yeh-Cheng Chen Shi-Jinn Horng T.-C. Wang Naixue Xiong Department of computer engineering Dongguan Polytechnic Dongguan P.R. China Department of computer science University of California Davis CA USA The School of Software and Microelectronic Northwestern Polytechnical University Xian P.R. China Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen P.R. China Institute of Information Management National Chiao Tung University School of Computer Science and Technology Tianjin University Tianjin P. R. China

ISBN: (纸本)9781538694046;9781538694039

Using the cloud technology with Smart Protect Network (SPN) to do file virus scanning. The overwhelming increase of population will lead to an increase network traffic usage. In most products, local cache mechanism is implemented for the purpose of reducing the network traffics. However, the database designed to store cache is limited, lot of times, cache will get purged when there are lots of queries sent and replaced by other newest queries. It is not an efficient by using traditional methodology to build or forming cache. In order to reduce the network traffic usage, the paper propose a solution, which utilize data mining technique with clustering concept, by gathering the current feedback data we have from our SPN, we are able to form these data in groups with similarity, and by deploying these data to client side, to achieve the reduction of traffic usage. In prototyping, this design for military communications can really reduce network traffic more than 20%. And the speed of file scanning time can faster more than 12%.

关键词： parallel architectures programming Data mining Optimization Telecommunication traffic

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