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Realizing Multioperations for Step Cached MP-SOCs

Realizing Multioperations for Step Cached MP-SOCs

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IEEE international symposium on System-on-Chip

作者： Martti Forsell Platform Architectures Team Oulu Finland

Recent advances in shared memory multiprocessor system-on-chip (MP-SOC) architectures include using special step caches to efficiently implement concurrent read concurrent write memory access. Unfortunately the existing step cache techniques do not support multioperations that can be used to speed up execution of a number of parallel algorithms by a logarithmic factor. This paper proposed an architectural technique for implementing multioperations on step cached MP-SOCs even if the associativity of caches is limited. The technique is based on simple active memory units, faster memory modules, and small processor-level memory blocks called scratchpads. The performance and area requirements of the proposed technique were evaluated on the parametrical MP-SOC framework. According to the evaluation the technique implements multioperations efficiently and provides a speed-up of 4.8 - 7.2 with respect baseline step cached systems and a speed-up of 3.7- 5.0 with respect to existing non-step cached systems with only a minor silicon are overhead

关键词： Read-write memory Yarn parallel algorithms Memory architecture Multiprocessing systems Silicon Message passing System-on-a-chip programming profession Hardware

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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Improved parameterized efficient FPGA implementations of par...

引用

IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Sami Hasan Said Boussakta Alex Yakovlev School of Electrical Electronic and Computer Engineering University of Newcastle UK

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. The improved parameterized FPGA implementation is a system-level abstraction of hardware-oriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time.

关键词： Delay Finite impulse response filter

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A software architecture for global address space communication on clusters: put/get on fast messages 98

A software architecture for global address space communicati...

引用

international symposium on High Performance Distributed Computing

作者： L.A. Giannini A.A. Chien Department of Computer Science University of Illinois Urbana-Champaign USA University of California San Diego La Jolla CA USA

ISBN: (纸本)9780818685798

Global address space parallel programming models can be an effective alternative to send/receive style communication, simplifying programming or code generation and increasing performance for certain application types. Traditionally, global address space mechanisms have been implemented in hardware in order to provide the necessary communication performance and responsiveness. However new high performance cluster messaging systems now allow global address space mechanisms to be realized efficiently in software. We describe a high performance one sided communication model that is implemented as a software layer on top of the Illinois Fast Messages (FM) system. We evaluate several different software implementation architectures for the remote agent, characterizing their differing performance characteristics. Our Put/Get FM implementation achieves peak bandwidths for put/get operations of 67 MBytes/s, overheads of a few microseconds, and remote read latencies as low as 26 microseconds on a Myrinet connected PC cluster. This implementation was released publicly as part of HPVM 1.0 in August 1997, and is receiving significant usage. It has been used for an implementation of the Global Arrays library and also serves as a back-end target for PGI's commercial HPF compiler.

关键词： Software architecture Software performance parallel programming Delay Application software Hardware Communication system software Computer architecture Bandwidth Libraries

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parallel, Portable algorithms for Distance-2 Maximal Independent Set and Graph Coarsening

Parallel, Portable Algorithms for Distance-2 Maximal Indepen...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Brian Kelley Sivasankaran Rajamanickam Sandia National Laboratories Albuquerque New Mexico U.S.A

Given a graph, finding the distance-2 maximal independent set (MIS-2) of the vertices is a problem that is useful in several contexts such as algebraic multigrid coarsening or multilevel graph partitioning. Such multilevel methods rely on finding the independent vertices so they can be used as seeds for aggregation in a multilevel scheme. We present a parallel MIS-2 algorithm to improve performance on modern accelerator hardware. This algorithm is implemented using the Kokkos programming model to enable performance portability. We demonstrate the portability of the algorithm and the performance on a variety of architectures (x86/ARM CPUs and NVIDIA/AMD GPUs). The resulting algorithm is also deterministic, producing an identical result for a given input across all of these platforms. The new MIS-2 implementation outperforms implementations in state of the art libraries like CUSP and ViennaCL by 3-8x while producing similar quality results. We further demonstrate the benefits of this approach by developing parallel graph coarsening scheme for two different use cases. First, we develop an algebraic multigrid (AMG) aggregation scheme using parallel MIS-2 and demonstrate the benefits as opposed to previous approaches used in the MueLu multigrid package in Trilinos. We also describe an approach for implementing a parallel multicolor “cluster” Gauss-Seidel preconditioner using this MIS-2 coarsening, and demonstrate better performance with an efficient, parallel, mul-ticolor Gauss-Seidel algorithm.

关键词： Distributed processing Clustering algorithms programming Libraries Hardware Partitioning algorithms

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An element-based concurrent partitioner for unstructured finite element meshes

An element-based concurrent partitioner for unstructured fin...

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international symposium on parallel Processing

作者： H.Q. Ding R.D. Ferraro Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA

A concurrent partitioner for partitioning unstructured finite element meshes on distributed memory architectures is developed. The partitioner uses an element-based partitioning strategy. Its main advantage over the more conventional node-based partitioning strategy is its modular programming approach to the development of parallel applications. The partitioner first partitions element centroids using a recursive inertial bisection algorithm. Elements and nodes then migrate according to the partitioned centroids, using a data request communication template for unpredictable incoming messages. Our scalable implementation is contrasted to a non-scalable implementation which is a straightforward parallelization of a sequential partitioner. The algorithms adopted in the partitioner scale logarithmically, as confirmed by actual timing measurements on the Intel Delta on up to 512 processors for scaled size problems.

关键词： Partitioning algorithms Finite element methods Memory architecture parallel programming Timing Size measurement

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Use of a functional programming model in fault tolerant parallel processing

Use of a functional programming model in fault tolerant para...

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international symposium on Fault-Tolerant Computing (FTCS)

作者： R. Harper G. Nagle M.A. Serrano System Architectures Division Charles Stark Draper Laboratories Inc. Cambridge MA USA

In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper fault-tolerant parallel processor (FTPP). When used in conjunction with the FTPP's fault-detection and masking capabilities, this implementation results in a graceful degradation of system performance after faults. Three graceful degradation algorithms are presented. A user interface has been implemented which requires minimal cognitive overhead by the application programmer, masking such complexities as the system's redundancy, distributed nature, variable complement of processing resources, load balancing, fault occurrence, and recovery. This user interface is described and its use demonstrated.< >

关键词： Functional programming Fault tolerance Degradation Load management User interfaces Concurrent computing Distributed computing Checkpointing Computer errors System performance

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A communication+computation load balanced loop partitioning method

A communication+computation load balanced loop partitioning ...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Pande School of Electrical Engineering and Computer Science Ohio University Athens OH USA

We present an iteration and data partitioning approach for DOALL loops on distributed memory systems. The method first examines the highest amount of parallelism (available parallelism) which could be potentially exploited in a loop nest. It then examines the amount of communication overhead which can potentially nullify the benefits due to parallelism and attempts to maximally eliminate the communication to minimize the loop completion time by trading parallelism to a minimal extent. This is achieved by determining the directions of iteration space partitioning which result in minimum communication. Finally, in order to generate a load balanced partition with respect to computation+communication, the method uses a new larger partition owns rule to distribute the underlying data. Necessary theoretical framework has been developed and the merit of the method is shown through a performance evaluation on Cray T3D.

关键词： parallel processing Computer science Distributed computing programming Data communication Distribution functions Costs Partitioning algorithms

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Exploiting spatial architectures for edit distance algorithms

Exploiting spatial architectures for edit distance algorithm...

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IEEE international symposium on Performance Analysis of Systems and Software

作者： Jesmin Jahan Tithi Neal C. Crago Joel S. Emer Stony Brook University VSSAD Intel Corporation VSSAD CSAIL MIT

In this paper, we demonstrate the ability of spatial architectures to significantly improve both runtime performance and energy efficiency on edit distance, a broadly used dynamic programming algorithm. Spatial architectures are an emerging class of application accelerators that consist of a network of many small and efficient processing elements that can be exploited by a large domain of applications. In this paper, we utilize the dataflow characteristics and inherent pipeline parallelism within the edit distance algorithm to develop efficient and scalable implementations on a previously proposed spatial accelerator. We evaluate our edit distance implementations using a cycle-accurate performance and physical design model of a previously proposed triggered instruction-based spatial architecture in order to compare against real performance and power measurements on an x86 processor. We show that when chip area is normalized between the two platforms, it is possible to get more than a 50× runtime performance improvement and over 100× reduction in energy consumption compared to an optimized and vectorized x86 implementation. This dramatic improvement comes from leveraging the massive parallelism available in spatial architectures and from the dramatic reduction of expensive memory accesses through conversion to relatively inexpensive local communication.

关键词： Computer architecture Pipelines Field programmable gate arrays parallel processing Signal processing algorithms Matrix converters Dynamic programming

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A reconfigurable architecture for scanning biosequence databases

A reconfigurable architecture for scanning biosequence datab...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： T. Oliver B. Schmidt D.L. Maskell A.P. Vinod School of Computer Engineering Nanyang Technological University Singapore

Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithms exist for this problem, the required scanning time is still very high. The scan time requirements are likely to become even more severe because of the rapid growth in size of these databases. Thus, finding fast solutions is of high importance to research in this area. We present a new approach to biosequence database scanning using reconfigurable FPGA-based hardware platforms to gain high performance at low cost. To derive an efficient mapping onto this type of architecture, we have designed fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query. This results in an implementation with significant runtime savings on a standard FPGA.

关键词： Reconfigurable architectures Databases Proteins Dynamic programming Heuristic algorithms Hardware Performance gain Costs Process design parallel processing

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Development of Control for a Serpentine Robot

Development of Control for a Serpentine Robot

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IEEE international symposium on Computational Intelligence in Robotics and Automation (CIRA)

作者： William R. Hutchison Betsy J. Constantine Johann Borenstein Jerry Pratt Behavior Systems Boulder CO USA University of Michigan Ann Arbor MI USA Yobotics Inc. Cincinnati OH USA

This paper describes the development and testing of control of the OmniTread OT-4 robot by the seventh generation (7G) control system. Control of OT-4 was developed in the Yobotics 3D simulator by an iterative process combining genetic algorithm, learning and analytic programming techniques. The control system developed in simulation was tested by controlling the real OT-4 robot in the laboratory. The performance of the real OT-4 robot under 7G control on stairs, parallel bars, a slalom course, and stairs with obstacles corresponded well to the simulated performance on which development of the control system was based.

关键词： Control system synthesis System testing Control systems Analytical models Genetic algorithms Algorithm design and analysis Robot programming Laboratories parallel robots Robot control

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