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Partitioning and scheduling for parallel image processing operations

Partitioning and scheduling for parallel image processing op...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Cheolwhan Lee Tao Yang Yuan-Fang Wang Department of Computer Science University of California Santa Barbara CA USA

ISBN: (纸本)0818671955

Many computer vision and image processing (CVIP) operations can be represented as a sequence of tasks with nested loops, specified by the visual programming language Khoros. This paper addresses the automatic partitioning and scheduling of such operations on distributed memory multiprocessors. The major difficulties in determining the optimal image data distribution for each task are that the number of processors available and the size of the input image may vary at the run time, and the cost of some image processing operations may be data-dependent. This paper proposes a compile-time processor assignment and data partitioning scheme that optimizes the average run-time performance of task chains with nested loops by considering the data redistribution overheads and possible run-time parameter variations. This paper presents the theoretical analysis and experimental results on a Meiko CS-2 distributed memory machine.

关键词： Image processing Processor scheduling Runtime Partitioning algorithms Dynamic scheduling Computer science Cost function Computer vision Concurrent computing Distributed computing

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A communication+computation load balanced loop partitioning method

A communication+computation load balanced loop partitioning ...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Pande School of Electrical Engineering and Computer Science Ohio University Athens OH USA

We present an iteration and data partitioning approach for DOALL loops on distributed memory systems. The method first examines the highest amount of parallelism (available parallelism) which could be potentially exploited in a loop nest. It then examines the amount of communication overhead which can potentially nullify the benefits due to parallelism and attempts to maximally eliminate the communication to minimize the loop completion time by trading parallelism to a minimal extent. This is achieved by determining the directions of iteration space partitioning which result in minimum communication. Finally, in order to generate a load balanced partition with respect to computation+communication, the method uses a new larger partition owns rule to distribute the underlying data. Necessary theoretical framework has been developed and the merit of the method is shown through a performance evaluation on Cray T3D.

关键词： parallel processing Computer science Distributed computing programming Data communication Distribution functions Costs Partitioning algorithms

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Exploiting spatial architectures for edit distance algorithms

Exploiting spatial architectures for edit distance algorithm...

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IEEE international symposium on Performance Analysis of Systems and Software

作者： Jesmin Jahan Tithi Neal C. Crago Joel S. Emer Stony Brook University VSSAD Intel Corporation VSSAD CSAIL MIT

In this paper, we demonstrate the ability of spatial architectures to significantly improve both runtime performance and energy efficiency on edit distance, a broadly used dynamic programming algorithm. Spatial architectures are an emerging class of application accelerators that consist of a network of many small and efficient processing elements that can be exploited by a large domain of applications. In this paper, we utilize the dataflow characteristics and inherent pipeline parallelism within the edit distance algorithm to develop efficient and scalable implementations on a previously proposed spatial accelerator. We evaluate our edit distance implementations using a cycle-accurate performance and physical design model of a previously proposed triggered instruction-based spatial architecture in order to compare against real performance and power measurements on an x86 processor. We show that when chip area is normalized between the two platforms, it is possible to get more than a 50× runtime performance improvement and over 100× reduction in energy consumption compared to an optimized and vectorized x86 implementation. This dramatic improvement comes from leveraging the massive parallelism available in spatial architectures and from the dramatic reduction of expensive memory accesses through conversion to relatively inexpensive local communication.

关键词： Computer architecture Pipelines Field programmable gate arrays parallel processing Signal processing algorithms Matrix converters Dynamic programming

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A distributed hierarchical programming model for heterogeneous cluster of SMPs

A distributed hierarchical programming model for heterogeneo...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： T. Rauber G. Runger S. Trautmann Fakultät für Mathematik und Physik Universität Bayreuth Bayreuth Germany Fakultät für Informatik Technische Universität Chemnitz-Zwickau Chemnitz Germany

Cluster systems are getting increasingly popular since they provide large computational power at a reasonable price. The cluster nodes are often SMP with a small number of processors that can access a shared address space. The nodes are connected by a network like Myrinet or SCI, so the global address space is distributed. In this paper, we present a new programming model for such clusters of SMP. The model allows the programmer to adapt his program to the two-level structure of the address space by providing a micro-level and a macro-level. The micro-level allows a thread formulation of multiprocessor tasks that are executed within a node of the cluster system. The macro-level allows the hierarchical structuring of multiprocessor-tasks according to the structure of the algorithm using message passing for data-exchange. We demonstrate the usefulness of the approach by runtime tests on several cluster systems with different node architectures and different interconnection networks.

关键词： Switched-mode power supply Libraries Runtime parallel machines Yarn Multiprocessor interconnection networks Power system modeling programming profession Clustering algorithms Message passing

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The Multicomputer Toolbox/spl minus/first-generation scalable libraries

The Multicomputer Toolbox/spl minus/first-generation scalabl...

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Annual Hawaii international Conference on System Sciences (HICSS)

作者： Skjellum Leung Smith Falgout Still Baldwin Computer Science Department & NSF Engineering Research Center Mississippi State University MS USA Northeast Parallel Architectures Center Syracuse University USA Numerical Mathematics Group Lawrence Livemore National Laboratory UK University of Illinois Urbana-Champaign USA

"First-generation" scalable parallel libraries have been achieved, and are maturing, within the Multicomputer Toolbox. The Toolbox includes sparse, dense, iterative linear algebra, a stiff ODE/DAE solver, and an open software technology for additional numerical algorithms. We have devised C-based strategies for useful classes of distributed data structures, including distributed matrices and vectors. The underlying Zip code message passing system has enabled process-grid abstractions of multicomputers, communication contexts, and process groups, all characteristics needed for building scalable libraries, and scalable application software. A data-distribution-independent approach to building scalable libraries is needed so that applications do not unnecessarily have to redistribute data at high expense. We discuss the strategy used for implementing data-distribution-independent mappings. We also indicate that data-distribution-independent algorithms are sometimes more efficient than fixed-data-distribution counterparts, because redistribution of data can be avoided, and that this question is strongly application dependent.< >

关键词： parallel machines parallel programming Distributed computing Data structures Linear algebra

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Development of Control for a Serpentine Robot

Development of Control for a Serpentine Robot

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IEEE international symposium on Computational Intelligence in Robotics and Automation (CIRA)

作者： William R. Hutchison Betsy J. Constantine Johann Borenstein Jerry Pratt Behavior Systems Boulder CO USA University of Michigan Ann Arbor MI USA Yobotics Inc. Cincinnati OH USA

This paper describes the development and testing of control of the OmniTread OT-4 robot by the seventh generation (7G) control system. Control of OT-4 was developed in the Yobotics 3D simulator by an iterative process combining genetic algorithm, learning and analytic programming techniques. The control system developed in simulation was tested by controlling the real OT-4 robot in the laboratory. The performance of the real OT-4 robot under 7G control on stairs, parallel bars, a slalom course, and stairs with obstacles corresponded well to the simulated performance on which development of the control system was based.

关键词： Control system synthesis System testing Control systems Analytical models Genetic algorithms Algorithm design and analysis Robot programming Laboratories parallel robots Robot control

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A multiprocessor architecture for the massively parallel model GCA 06

A multiprocessor architecture for the massively parallel mod...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： W. Heenes R. Hoffmann J. Jendrsczok TU Darmstadt FB Informatik FG Rechnerarchitektur Darmstadt Germany

ISBN: (纸本)9781424400546

The GCA (global cellular automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA model. In differentiation to the CA model the neighbors are not fixed and local, they are variable and global. The GCA model is applicable to a wide range of parallel algorithms. In this paper, a multiprocessor architecture for the massively parallel GCA model is presented. In contrast to a special purpose implementation of a GCA algorithm the multiprocessor system allows the implementation in a flexible way through programming. The architecture mainly consists of a number of cell processors and a network. The cell processors are dedicated RISC processors, the network is a crossbar implemented with multiplexers. Only read-accesses through the network are necessary in the GCA model leading to a simplified structure. A system with 32 processors was implemented as a prototype on a FPGA. The analysis and implementation results have shown that the performance of the system scales very well with the number of processors

关键词： Computer architecture Hardware Field programmable gate arrays parallel architectures parallel algorithms Multiprocessing systems Reduced instruction set computing Multiplexing Prototypes Performance analysis

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parallel coprocessor architectures for molecular dynamics simulation: a case study in design space exploration

Parallel coprocessor architectures for molecular dynamics si...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： M. Gerber T. Gossi Computer Engineering and Networks Lab Swiss Federal Institute of Technology Zurich Switzerland Electronics Lab Swiss Federal Institute of Technology Zurich Switzerland

The purpose of the paper is to describe a new semi-automated design space exploration method based on genetic programming. A new control/dataflow specification method is proposed as well as appropriate models for hardware parts and algorithms. With this method we are able to test many different hardware architectures and algorithms against cost, speed, computation time and other constraints within a very short time. The remaining manual work is to exploit the model parameters of the components of the architecture and the algorithm. In contrast to other approaches our method is suited for embedded and distributed systems. The method, models and application are explained in detail by means of a comprehensive case study.

关键词： Coprocessors Computer aided software engineering Hardware Computer architecture Computational modeling Intelligent networks Space technology Space exploration Acceleration Pipelines

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Surface reconstruction in parallel

Surface reconstruction in parallel

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Talele T. Johnson P.E. Livadas Computer ancl Information Sciences Department University of Florida Gainesville FL USA

By exploiting the structure of a directed toroidal graph, the authors have developed a parallel solution to find the shortest path. A parallel dynamic programming solution to finding the minimum cost path is presented. First the authors map the toroidal graph to a planar graph, whose structure is exploited to form a parallel algorithm suitable for a message-passing parallel architecture. The problem has applications in surface reconstruction, where contours of a surface are represented as graphs. Finding the shortest-path in these graphs corresponds to finding a best-fit surface over the contours. By parallelizing the solution, the authors have obtained a significant speedup to a computationally intensive problem. Since generic message passing is used for interprocessor communication, the proposed algorithm can be implemented in any distributed or parallel environment. In a heterogeneous environment, relative processor speed and memory would have to be considered for load balancing.< >

关键词： Surface reconstruction Tiles Medical diagnostic imaging parallel algorithms Surface fitting Cost function Dynamic programming parallel architectures Concurrent computing Mathematics

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Cyclic networks: A family of versatile fixed-degree interconnection architectures

Cyclic networks: A family of versatile fixed-degree intercon...

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international symposium on parallel Processing

作者： C.-H. Yeh B. Parhami Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

In this paper, we propose a new family of interconnection networks, called cyclic networks (CNs), in which an intercluster connection is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degrees of basic CNs are independent of system size, but can vary from a small constant (e.g., 3) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. The diameters of suitably constructed CNs can be asymptotically optimal within their lower bounds, given the degrees. We show that packet routing and ascend/descend algorithms can be performed in /spl Theta/(log/sub d/ N) communication steps on some CNs with N nodes of degree /spl Theta/(d). Moreover CNs can also efficiently emulate homogeneous product networks (e.g., hypercubes and high dimensional meshes). As a consequence, we obtain a variety of efficient algorithms on such networks, thus proving the versatility of CNs.

关键词： Costs Hypercubes Multiprocessor interconnection networks Computer architecture Routing Network topology Algorithm design and analysis parallel programming Scalability Hardware

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