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High-Performance Fortran and possible extensions to support conjugate gradient algorithms 96

High-Performance Fortran and possible extensions to support ...

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international symposium on High Performance Distributed Computing

作者： K. Dincer G.C. Fox K. Hawick School of Computer and Information Sciences Northeast Parallel Architectures Center Syracuse University NY USA

ISBN: (纸本)9780818675829

Evaluates the High Performance Fortran (HPF) language for the compact expression and efficient implementation of conjugate-gradient iterative matrix-solvers on high-performance computing and communications (HPCC) platforms. We discuss the use of intrinsic functions, data distribution directives and explicitly parallel constructs to optimize performance by minimizing communications requirements in a portable manner. We focus on implementations using the existing HPF definitions but also discuss issues arising that may influence a revised definition for HPF-2. Some of the codes discussed are available on the World Wide Web at http://***/hpfa/, along with other educational and discussion material related to applications in HPF.

关键词： Character generation Sparse matrices Concurrent computing programming profession Equations Iterative algorithms Physics computing Distributed computing Program processors Fluid dynamics

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A multiprocessor architecture for the massively parallel model GCA 06

A multiprocessor architecture for the massively parallel mod...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： W. Heenes R. Hoffmann J. Jendrsczok TU Darmstadt FB Informatik FG Rechnerarchitektur Darmstadt Germany

ISBN: (纸本)9781424400546

The GCA (global cellular automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA model. In differentiation to the CA model the neighbors are not fixed and local, they are variable and global. The GCA model is applicable to a wide range of parallel algorithms. In this paper, a multiprocessor architecture for the massively parallel GCA model is presented. In contrast to a special purpose implementation of a GCA algorithm the multiprocessor system allows the implementation in a flexible way through programming. The architecture mainly consists of a number of cell processors and a network. The cell processors are dedicated RISC processors, the network is a crossbar implemented with multiplexers. Only read-accesses through the network are necessary in the GCA model leading to a simplified structure. A system with 32 processors was implemented as a prototype on a FPGA. The analysis and implementation results have shown that the performance of the system scales very well with the number of processors

关键词： Computer architecture Hardware Field programmable gate arrays parallel architectures parallel algorithms Multiprocessing systems Reduced instruction set computing Multiplexing Prototypes Performance analysis

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Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Decentralized in-order execution of a sequential task-based ...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Charly Castes Emmanuel Agullo Olivier Aumage Emmanuelle Saillard Inria - LaBRI EPFL Bordeaux France Inria - LaBRI Bordeaux France

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with advanced runtime systems allow the programmer to write a sequential algorithm independently of the hardware architecture in a productive and portable manner, and let a third party software layer -the runtime system- deal with the burden of scheduling a correct, parallel execution of that algorithm to ensure performance. Many HPC algorithms have successfully been implemented following this paradigm, as a testimony of its effectiveness. Developing algorithms that specifically require fine-grained tasks along this model is still considered prohibitive, however, due to per-task management overhead [1], forcing the programmer to resort to a less abstract, and hence more complex “task+X” model. We thus investigate the possibility to offer a tailored execution model, trading dynamic mapping for efficiency by using a decentralized, conservative in-order execution of the task flow, while preserving the benefits of relying on the sequential task-based programming model. We propose a formal specification of the execution model as well as a prototype implementation, which we assess on a shared-memory multicore architecture with several synthetic workloads. The results show that under the condition of a proper task mapping supplied by the programmer, the pressure on the runtime system is significantly reduced and the execution of fine-grained task flows is much more efficient.

关键词： Runtime Computational modeling Software algorithms Computer architecture programming Hardware Software

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Integer Linear programming Method for Spatial Temporal Mapping of the Viterbi Decoder

Integer Linear Programming Method for Spatial Temporal Mappi...

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Proceedings of 2006 IEEE international symposium on Circuits and Systems,Volume 4

作者： Appaya Devaraj, S. Nastooh Avessta Department of Information Technology University of Turku Turku Finland

Array processors are gaining importance as fabrication technology scales down. Thus a simple and systematic method to implement algorithms in array architectures is desirable. In this paper a general Integer Linear Program (ILP) is formulated to minimize computation time and interconnection length. The ILP is solved with various constraints on the parallel computation time and interconnect space. Different cost functions as desired by the designer can be added to the optimization process. Viterbi decoder is considered as a case study. Optimum array architecture is obtained using the proposed ILP.

关键词： Integer linear programming Viterbi algorithm Decoding Cost function Fabrication Convolutional codes Design optimization Systolic arrays Information technology Computer architecture

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DSP performance evaluation for motion estimation

DSP performance evaluation for motion estimation

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international symposium on Signal Processing and Its Applications (ISSPA)

作者： L. Louro P. Santos N. Rodrigues V. Silva S. Faria Instituto de Telecomunicações DEEC Pólo II da Universidade de Coimbra Coimbra Portugal Escola Superior de Tecnologia e Gestão Institnto Politécnico de Leíria Leiria Portugal

In this paper, we analyze the performance of the floating point digital signal processor (DSP) TMS320C6711 for an implementation of video coding motion. Two relevant motion estimation techniques were implemented: BMA (block matching algorithm) and BMGT (block matching using geometric transforms). These have been combined with fast block matching algorithms to speed up the process. In order to increase the DSP performance, we have optimized some programming mechanisms like: the level of code parallelism, hand designed assembly code and an efficient usage of internal memory as cache. This implementation has shown that real-time motion estimation of BMA type, can be implemented in this DSP. However. BMGT type motion estimation cannot be done by one DSP alone in-real time applications, due to its high computational complexity.

关键词： Digital signal processing Motion estimation Signal processing algorithms Signal analysis Performance analysis Digital signal processors Video coding Motion analysis Design optimization parallel programming

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User level DB: a debugging API for user-level thread libraries

User level DB: a debugging API for user-level thread librari...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Kevin Pouget Marc Pérache Patrick Carribault Hervé Jourdren CEA DIF Arpajon France

ISBN: (纸本)9781424465330

With the advent of the multicore era, parallel programming is becoming ubiquitous. Multithreading is a common approach to benefit from these architectures. Hybrid M:N libraries like MultiProcessor Communication (MPC) or MARCEL reach high performance expressing fine-grain parallelism by mapping M user-level threads onto N kernel-level threads. However, such implementations skew the debuggers' ability to distinguish one thread from another, because only kernel threads can be handled. SUN MICROSYSTEMS' THREAD_DB API is an interface between the debugger and the thread library allowing the debugger to inquire for thread semantics details. In this paper we introduce the USER LEVEL DB (ULDB) library, an implementation of the THREAD_DB interface abstracting the common features of user-level thread libraries. ULDB gathers the generic algorithms required to debug threads and provide the thread library with a small and focused interface. We describe the usage of our library with widely-used debuggers (GDB, DBX) and the integration into a user-level thread library (GNUPTH) and two high-performance hybrid libraries (MPC, MARCEL).

关键词： Debugging Libraries Multithreading Kernel Clocks Multicore processing parallel programming parallel processing Surges

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Cyclic networks: A family of versatile fixed-degree interconnection architectures

Cyclic networks: A family of versatile fixed-degree intercon...

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international symposium on parallel Processing

作者： C.-H. Yeh B. Parhami Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

In this paper, we propose a new family of interconnection networks, called cyclic networks (CNs), in which an intercluster connection is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degrees of basic CNs are independent of system size, but can vary from a small constant (e.g., 3) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. The diameters of suitably constructed CNs can be asymptotically optimal within their lower bounds, given the degrees. We show that packet routing and ascend/descend algorithms can be performed in /spl Theta/(log/sub d/ N) communication steps on some CNs with N nodes of degree /spl Theta/(d). Moreover CNs can also efficiently emulate homogeneous product networks (e.g., hypercubes and high dimensional meshes). As a consequence, we obtain a variety of efficient algorithms on such networks, thus proving the versatility of CNs.

关键词： Costs Hypercubes Multiprocessor interconnection networks Computer architecture Routing Network topology Algorithm design and analysis parallel programming Scalability Hardware

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dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core

dIP: A Non-intrusive Debugging IP for Dynamic Data Race Dete...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Chi-Neng Wen Shu-Hsuan Chou Tien-Fu Chen National Chung Cheng University Chiayi Taiwan

Traditional debug facilities are limited in providing debugging requirements for multicore parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. This work presents a fast and feasible hardware-assistant solution for many-core non-intrusive debugging. The key idea is to keep tracks of data accesses of shared memory areas and their lock synchronization activities by proposed data structures in proposed debugging IP (dIP). A page-based shared variable cache is provided to keep shared variables as long as possible, and an inexpensive pluggable off-chip RAM can eliminate the false-positive rate efficiently. To decrease the debugging traffic block, this work provides a thread library to specify shared memory/lock events and transmit those events to the dIP by a small proper hardware co-processor (eXtend dIP) of each core. Our experimental result shows the debugging traffic block (worse-case) by increasing cores, and adding tolerance buffers in XdIP can efficiently ease off. Moreover, the real workloads (SPLASH-2, MPEG-4, and H.264) are executed by the dIP non-instructive race-detection with only 4.7%~12.2% slow down in average. Finally, the hardware cost of dIP is also low when the growing of many-core.

关键词： Random access memory Hardware Multicore processing parallel programming Computer bugs Software debugging Data structures Read-write memory Yarn Libraries

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LinROS: A Linux-Based Runtime System for Reconfigurable MPSoCs

LinROS: A Linux-Based Runtime System for Reconfigurable MPSo...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jens Rettkowski Philipp Wehner Evgheni Cutiscev Diana Göhringer Application-Specific Multi-Core Architectures (MCA) Group Ruhr-University Bochum (RUB) Bochum Germany

Modern FPGA-based Multiprocessor Systems-on-Chip (MPSoCs) support dynamic reconfiguration of processing elements (PEs) such as processors and accelerators. The reconfiguration improves the flexibility of the system due to the dynamic and partial exchange of PEs. However, the design of reconfigurable MPSoCs leads also to higher complexity in programming due to the huge design space. To bridge this gap, this paper presents a runtime system consisting of a software layer called LinROS. It dynamically schedules and reconfigures PEs. LinROS uses a novel Linux device driver that automatically manages the software and hardware of the reconfigurable MPSoC at runtime. In addition, an IP core developed for LinROS facilitates an easy hardware integration of PEs using High-Level-Synthesis tools such as VivadoHLS. Data exchange between PEs is managed by the IP core. The entire system is evaluated on a Xilinx Zynq SoC performing image processing algorithms. The results show a negligible overhead of the scheduling while the programming of reconfigurable MPSoCs is significantly simplified by the device driver. Furthermore, the hardware design of PEs is also simplified due to the High-Level Synthesis.

关键词： Program processors Hardware Linux Operating systems Runtime programming

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High-Performance Energy-Efficient Recursive Dynamic programming with Matrix-Multiplication-Like Flexible Kernels

High-Performance Energy-Efficient Recursive Dynamic Programm...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Jesmin Jahan Tithi Pramod Ganapathi Aakrati Talati Sonal Aggarwal Rezaul Chowdhury Department of Computer Science Stony Brook University New York USA

Dynamic programming (DP) problems arise in wide range of application areas spanning from logistics to computational biology. In this paper, we show how to obtain high-performing parallel implementations for a class of Problems by reducing them to highly utilizable flexible kernels through cache-oblivious recursive divide- and-conquer(CORDAC). We implement parallel CORDAC algorithms for four non-trivial DP problems, namely the parenthesization problem, Floyd-Warshall's all-pairs shortest path (FW-APSP), sequence alignment with general gap penalty (gap problem)and protein accordion folding. To the best of our knowledge our algorithms for protein accordion folding and the gap problem are novel. All four algorithms have asymptotically optimal cache performance, and all but FW-APSP have asymptotically more parallelism than their looping counterparts. We show that the base cases of our CORDAC algorithms are predominantly matrix-multiplication-like (MM-like) flexible kernels that expose many optimization opportunities not offered by traditional looping DP codes. As a result, one can obtain highly efficient DP implementations by optimizing those flexible kernels only. Our implementations achieve 5 -- 150× speedup over their standard loop based DP counterparts while consuming order-of-magnitude less energy on modern multicore machines with 16 -- 32 cores. We also compareour implementations with parallel tiled codes generated by existing polyhedral compilers: Polly, PoCC and PLuTo, and show that our implementations run significantly faster. Finally, we present results on manicures (Intel Xeon Phi) and clusters of multicores obtained using simple extensions for SIMD and shared-distributed-shared-memory architectures, respectively, demonstrating the versatility of our approach. Our optimization approach is highly systematic and suitable for automation.

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