The authors introduce a formal approach for synthesis of parallelarchitectures. Four different forms are used to express the given algorithms: simultaneous recursion, recursion with respect to different variables, fi...
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The authors introduce a formal approach for synthesis of parallelarchitectures. Four different forms are used to express the given algorithms: simultaneous recursion, recursion with respect to different variables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting and required hardware. The approach is providing two main features: completeness and correctness.< >
parallelprogramming has to date remained inaccessible to the average scientific programmer. parallelprogramming languages are generally foreign to most scientific applications programmers who only speak Fortran. Aut...
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parallelprogramming has to date remained inaccessible to the average scientific programmer. parallelprogramming languages are generally foreign to most scientific applications programmers who only speak Fortran. Automatic parallelization techniques have so far proved unsuccessful in extracting large amounts of parallelism from sequential codes and do not encourage development of new, inherently parallelalgorithms. In addition, there is a lack of consistency of programmer interface across architectures which requires programmers to invest a lot of effort in porting code from one parallel machine to another. This paper discusses the object oriented Fortran language and support routines developed at Mississippi State in support of parallelizing complex field simulations. This interface is based on Fortran to ease its acceptance by scientific programmers and is implemented on top of the Unix operating system for portability.< >
The dynamic reconfiguration of the interconnection network is an advanced feature of some multicomputers to reduce the communication overhead. The authors present an algorithm for the dynamic reconfiguration of the ne...
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The dynamic reconfiguration of the interconnection network is an advanced feature of some multicomputers to reduce the communication overhead. The authors present an algorithm for the dynamic reconfiguration of the network. Reconfiguration is limited, preserving the original topology. Long distance message passing is minimized by positioning communication partners close to each other. The algorithm is transparent to the application programmer and is not restricted to a particular class of applications, being very well suited for parallel applications whose communication pattern varies over time. The paper also presents some simulation results, showing the benefits from the new reconfiguration algorithm.< >
The add-compare-select (ACS) loop operation in serial dynamic programming (DP) problems inherently limits the speed or the iteration period. The author shows that the ACS loop operation (although nonlinear) can exploi...
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The add-compare-select (ACS) loop operation in serial dynamic programming (DP) problems inherently limits the speed or the iteration period. The author shows that the ACS loop operation (although nonlinear) can exploit look-ahead. He uses techniques of look-ahead, decomposition, and incremental computation, and proposes fine-grain pipelined and parallelarchitectures for area-efficient high-speed VLSI implementation of DP problems. The word-level arithmetic implementation complexity of the architecture is proportional to the cube of the number of states of the DP problem, logarithmic in number of loop pipeline levels, linear in block size, and additive with respect to pipelining and block processing. The data-dependent nature of the quantization operation limits the opportunities to pipeline the quantizer loops. The author proposes an approach to transform the quantizer loop into an equivalent form that can exploit look-ahead. The transformed quantizer loop recursion is shown to be similar to the DP recursion, and variations of the DP processor architectures can be used for high-speed implementation of simple quantizer loops.< >
In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper...
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In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper fault-tolerant parallel processor (FTPP). When used in conjunction with the FTPP's fault-detection and masking capabilities, this implementation results in a graceful degradation of system performance after faults. Three graceful degradation algorithms are presented. A user interface has been implemented which requires minimal cognitive overhead by the application programmer, masking such complexities as the system's redundancy, distributed nature, variable complement of processing resources, load balancing, fault occurrence, and recovery. This user interface is described and its use demonstrated.< >
The authors review bit-level processor arrays and the common characteristics that make them ideal for VLSI and high-speed computations. Emphasis is on arrays that have been implemented rather than proposed architectur...
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The authors review bit-level processor arrays and the common characteristics that make them ideal for VLSI and high-speed computations. Emphasis is on arrays that have been implemented rather than proposed architectures. The essential features shared by these arrays, and those that differentiate them are characterized and used to develop a taxonomy for bit-level processor arrays. The authors also discuss programming tools, with an emphasis on RAB, a large program used to map a class of algorithms written in C onto bit-level processor arrays. The basic components and extensions to RAB are discussed. Directions of current research and design of bit-level processor array architectures and their programming environments are also briefly discussed.< >
A method for the programming and evaluation of parallel signal-processor architectures based on a data-flow representation of signal-processing algorithms is described. The constant data flow, which is a special prope...
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A method for the programming and evaluation of parallel signal-processor architectures based on a data-flow representation of signal-processing algorithms is described. The constant data flow, which is a special property of most signal-processing algorithms, allows the scheduling and resource allocation to be done at compile time, rather than at run time as in usual data-flow systems. It is therefore possible to describe arbitrary hardware configurations;a result that is closer to a realizable hardware solution is guaranteed. Therefore hardware requirements can be kept low. 7 refs.
This book constitutes the proceedings of the 11th internationalsymposium on Advanced parallel Processing Technologies, APPT 2015, held in Jinan, China, in August 2015. The 8 papers presented in this volume were caref...
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ISBN:
(数字)9783319232164
ISBN:
(纸本)9783319232157
This book constitutes the proceedings of the 11th internationalsymposium on Advanced parallel Processing Technologies, APPT 2015, held in Jinan, China, in August 2015.
The 8 papers presented in this volume were carefully reviewed and selected from 24 submissions. They deal with the recent advances in big data processing; parallelarchitectures and systems; parallel software; parallelalgorithms and applications; and distributed and cloud computing.
This book constitutes the refereed proceedings of the 11th internationalsymposium on parallelarchitectures, algorithms and programming, PAAP 2020, held in Shenzhen, China, in December 2020.
ISBN:
(数字)9789811600104
ISBN:
(纸本)9789811600098
This book constitutes the refereed proceedings of the 11th internationalsymposium on parallelarchitectures, algorithms and programming, PAAP 2020, held in Shenzhen, China, in December 2020.
This book constitutes the proceedings of the 12th internationalsymposium on Advanced parallel Processing Technologies, APPT 2017, held in Santiago de Compostela, Spain, in August 2017.;The 11 regular papers presented...
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ISBN:
(数字)9783319679525
ISBN:
(纸本)9783319679518
This book constitutes the proceedings of the 12th internationalsymposium on Advanced parallel Processing Technologies, APPT 2017, held in Santiago de Compostela, Spain, in August 2017.;The 11 regular papers presented in this volume were carefully reviewed and selected from 18 submissions. They deal with the recent advances in big data processing; parallelarchitectures and systems; parallel software; parallelalgorithms and artificial intelligence applications; and distributed and cloud computing.
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