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ieee workshop on signal processing systems, sips: design and implementation

IEEE Workshop on Signal Processing Systems, SiPS: Design and...

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2018 ieee workshop on signal processing systems, sips 2018

ISBN: (纸本)9781538663189

The proceedings contain 60 papers. The topics discussed include: extraction of fetal ECG from maternal abdominal record in the 3rd trimester of gestation using R-R interval windowing technique;energy modeling of cluster system;bandwidth efficient architectures for convolutional neural network;arithmetic computations based on chemical reaction networks;sparsity aware fast block LMS algorithms for MIMO radar imaging;design of iterative hybrid beamforming for multi-user mmWave massive MIMO systems;and efficient compressed landweber detector for massive MIMO.

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Contrastive Learning in Memristor-based Neuromorphic systems 37

Contrastive Learning in Memristor-based Neuromorphic Systems

引用

2024 International workshop on signal processing systems

作者： Merkel, Cory Ororbia, Alexander G. Rochester Inst Technol Brain Lab Rochester NY 14623 USA Rochester Inst Technol Neural Adapt Comp Lab Rochester NY 14623 USA

ISBN: (纸本)9798350373769;9798350373752

Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks, including their high energy inefficiency and long-criticized biological implausibility. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning. Our experimental simulations demonstrate that a hardware implementation of CSDP is capable of learning simple logic functions without the need to resort to complex gradient calculations.

关键词： conrastive learning hebbian memristor neuromorphic

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Hardware implementation of Soft Mapper/Demappers in Iterative EP-based Receivers 37

Hardware Implementation of Soft Mapper/Demappers in Iterativ...

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2024 International workshop on signal processing systems

作者： Schilling, Ian Fischer Sahin, Serdar Leroux, Camille Cipriano, Antonio Maria Jego, Christophe Univ Bordeaux Bordeaux INP IMS Lab UMR CNRS 5218 Bordeaux France Thales Gennevilliers France

ISBN: (纸本)9798350373769;9798350373752

This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture.

关键词： Expectation Propagation Frequency Domain Self-Iterated Linear Equalizer Analytical approximations architecture design FPGA prototyping

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Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator implementation for Reflection Optimization 37

Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communi...

引用

2024 International workshop on signal processing systems

作者： Kompostiotis, Dimitris Paliouras, Vassilis Univ Patras Elect & Comp Engn Dept Patras Greece

ISBN: (纸本)9798350373769;9798350373752

Sixth generation (6G) wireless networks envision new Internet-of-Things (IoT) applications that require faster and more secure data transmission. Reconfigurable intelligent surfaces (RISs) can improve physical-layer security in wireless communications by optimally reflecting incoming electromagnetic waves to benefit legitimate users (LUs) and simultaneously hinder eavesdroppers (ED). However, for low-latency data transmission and short-coherence-time wireless channels, optimizing the RIS configuration must be done extremely fast, thus requiring a hardware accelerator. In this paper, we consider a multi-input multiple-output (MIMO) RIS-enabled physical-layer security system and introduce a novel low-latency hardware accelerator to maximize the achievable secrecy rate by optimizing the RIS reflection coefficients. The proposed accelerator implements a Dinkelbach-based iterative algorithm, here modified for the MIMO case and to facilitate hardware implementation. Simulations reveal that high-quality solutions are obtained, compared to a theoretical upper limit. The proposed sub-1-ms latency accelerator is detailed, highlighting design choices that enable its fast operation under moderate resource requirements, and also meeting the real-time requirements of emerging 6G applications.

关键词： 6G Reconfigurable intelligent surfaces physical layer security MIMO FPGA-based hardware accelerator

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Box Decoding: A Low-Complexity Algorithm for MIMO Detection 37

Box Decoding: A Low-Complexity Algorithm for MIMO Detection

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2024 International workshop on signal processing systems

作者： Qureshi, Sheikh Faizan Damjancevic, Stefan A. Matus, Emil Utyansky, Dmitry van der Wolf, Pieter Fettweis, Gerhard P. Tech Univ Dresden Vodafone Chair Dresden Germany Synopsys Inc Sunnyvale CA USA Synopsys Inc Eindhoven Netherlands Barkhausen Inst Dresden Germany Tech Univ Dresden CeTI Dresden Germany

ISBN: (纸本)9798350373769;9798350373752

The selection of an algorithm for MIMO detection often involves a trade-off between detection performance and the efficiency of the implementation. Tree-based algorithms, such as Sphere Decoding (SD), offer superior performance compared to linear schemes like MMSE and ZF and non-linear schemes like successive interference cancellation (SIC). In the SD approach, the algorithm must select the most suitable branch at each tree node. Due to this conditional behavior, the number of computational steps is data-dependent and is only determined at run-time. Moreover, due to the sequential nature of the tree traversal, it is not well suited for parallel implementation on a modern vector DSP. Approaches like K-Best exist to address this challenge, but they remain computationally intense, especially for higher-order QAM modulations. We study the use case of the 5G-based IoT standard NR-Redcap, which requires a low-complexity baseband kernel implementation for a cost-effective modem design. We propose a novel MIMO detection scheme called Box Decoding, whose computational complexity does not depend on the QAM modulation order and offers a significant reduction in complexity compared to K-Best for our chosen use case. Furthermore, the algorithm doesn't necessitate the expensive sorting of candidate symbols, making it particularly appealing for implementation on contemporary vector Digital signal Processors (DSPs). Testing on a 64QAM modulation system for Redcap indicates negligible MIMO detection performance degradation compared to K-Best, with significantly lower complexity. For our use case, the Box Decoding algorithm proves to be a cost-effective implementation scheme for MIMO detection in 5G IoT modems, offering a 2dB SNR gain over MMSE-based SIC for an extra 23% of clock cycles consumed for this task on a 512-bit vector DSP.

关键词： Multi-antenna systems 5G new radio (NR) Redcap detection algorithms Vector DSP mobile communications.

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Proceedings - 2024 ieee workshop on signal processing systems, sips 2024

Proceedings - 2024 IEEE Workshop on Signal Processing System...

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37th ieee International workshop on signal processing systems, sips 2024

ISBN: (纸本)9798350373752

The proceedings contain 36 papers. The topics discussed include: evaluation of coarse-grained reconfigurable array for a dual mode OTFS-OFDM modulator;fast energy optimization of on-chip ECC memories;box decoding: a low-complexity algorithm for MIMO detection;HM-detect: a novel method for heart murmur detection and classification using machine learning and sound feature analysis;on the mismatch between the phase structure of all-pole-based synthetic vowels and natural vowels;QEEGNet: quantum machine learning for enhanced electroencephalography encoding;processing multi-layer perceptrons in-memory;hierarchical quantum control gates for functional MRI understanding;and noise identification for data-augmented physics-based state-space models.

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Message from the Conference Chairs: sips 2024

IEEE Workshop on Signal Processing Systems, SiPS: Design and...

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ieee workshop on signal processing systems, sips: design and implementation 2024年 x-xi页

作者： Cavallaro, Joseph R. McAllister, John Nurmi, Jari Boutellier, Jani Rice University United States Queen's University Belfast United Kingdom Tampere University Finland University of Vaasa Finland

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ieee workshop on signal processing systems, sips: design and implementation

IEEE Workshop on Signal Processing Systems, SiPS: Design and...

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2017 ieee International workshop on signal processing systems, sips 2017

ISBN: (纸本)9781538604465

The proceedings contain 58 papers. The topics discussed include: budget restricted incremental learning with pre-trained convolutional neural networks and binary associative memories;a modified gradient descent bit flipping decoding scheme for LDPC codes;a stochastic number representation for fully homomorphic cryptography;a reduction of circuit size of digital direct-driven speaker architecture using segmented pulse shaping technique;CRN-based design methodology for synchronous sequential logic;an efficient conjugate residual detector for massive MIMO systems;analysing the performance of divide-and-conquer sequential matrix diagonalisation for large broadband sensor arrays;blind detection of polar codes;a discriminative spectral-temporal feature set for motor imagery classification;advanced wireless digital baseband signal processing beyond 100 Gbit/S;a split pre-conditioned conjugate gradient method for massive MIMO detection;a joint spatial texture analysis/watermarking system for digital image authentication;digital self-interference cancellation in inter-band carrier aggregation transceivers: algorithm and digital implementation perspectives;design space exploration of dataflow-based Smith-Waterman FPGA implementations;and DVFS based power management for LDPC decoders with early termination.

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2022 ieee workshop on signal processing systems, sips 2022

2022 IEEE Workshop on Signal Processing Systems, SiPS 2022

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36th ieee workshop on signal processing systems, sips 2022

ISBN: (纸本)9781665485241

The proceedings contain 32 papers. The topics discussed include: Bayesian optimization for simultaneous deconvolution of room impulse responses;beam alignment for the cell-free mmWave massive MU-MIMO uplink;ultra-fast machine learning inference through c code generation for tangled program graphs;cosmic: a real-time platform for signal processing pipelines;common spatial pattern with deep learning for fetal heart rate monitoring;virtual triggering: a technique to segment cryptographic processes in side-channel traces;statistical and morphological component separation of foregrounds in convolved HI skymaps;multi-factor pruning for recursive projection-aggregation decoding of RM codes;and an adjustable farthest point sampling method for approximately-sorted point cloud data.

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design and implementation of Autoencoder-LSTM Accelerator for Edge Outlier Detection

Design and Implementation of Autoencoder-LSTM Accelerator fo...

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35th ieee workshop on signal processing systems (ieee sips)

作者： Mohamed, Nadya A. Cavallaro, Joseph R. Rice Univ Dept Elect & Comp Engn POB 1892 Houston TX 77251 USA

ISBN: (纸本)9781665401449

Sensors are used to monitor various parameters in many real-world applications. Sudden changes in the underlying patterns of the sensors readings may represent events of interest. Therefore, event detection, an important temporal version of outlier detection, is one of the primary motivating applications in sensor networks. This work describes the implementation of a real-time outlier detection that uses an Autoencoder-LSTM neural-network accelerator implemented on the Xilinx PYNQ-Z1 development board. The implemented accelerator consists of a fine-tuned Autoencoder to extract the latent features in sensor data followed by a Long short-term memory (LSTM) network to predict the next step and detect outliers in real-time. The implemented design achieves 2.06 ms minimum latency and 85.9 GOp/s maximum throughput. The low latency and 0.25 W power consumption of the Autoencoder-LSTM outlier detector makes it suitable for resource-constrained computing platforms.

关键词： Accelerator FPGA embedded systems Autoencoder LSTM outliers CORDIC

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