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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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A frequency channelized adaptive wideband receiver for high-speed links

A frequency channelized adaptive wideband receiver for high-...

引用

ieee workshop on signal processing systems

作者： Feng, L Namgoong, W Univ So Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)0780377958

A new class of high-speed link receiver architecture that operates at a fraction of the on-chip clock frequency is proposed. Instead of time-interleaving multiple ADCs as is conventionally done, the received signal is channelized into multiple frequency subbands using a bank of mixers and lowpass filters. The proposed receiver architecture enjoys numerous implementation advantages. Based on the frequency channelized signals, an adaptive synchronization/detection scheme is described. An adaptive solution is necessary since the propagation channel and the analog analysis filters are generally not perfectly known and the symbol rate is incommensurate with the free running ADC sampling rate.

关键词： Band pass filters Bandwidth Channel bank filters Clocks Filter bank Frequency synchronization Sampling methods signal synthesis Transmitters Wideband

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implementation of the 2D DCT using a Xilinx XC6264 FPGA

Implementation of the 2D DCT using a Xilinx XC6264 FPGA

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Trainor, DW Heron, JP Woods, RF Integrated Silicon Systems Ltd Belfast United Kingdom

ISBN: (纸本)0780338065

This paper presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.

关键词： Logic design

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VLSI implementation of multiplier-free low power baseband filter for CDMA systems

VLSI implementation of multiplier-free low power baseband fi...

引用

ieee workshop on signal processing systems

作者： Lian, Y Yu, X Natl Univ Singapore Dept Elect & Comp Engn Singapore 119260 Singapore

ISBN: (纸本)0780377958

A multiplier-free baseband filter is proposed for the low power VLSI implementation in a Code Division Multiple Access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter structure involving a pair of even and odd length FIR filter with same bandedges. It is shown by means of example that the new structure not only achieves 45.8% savings in the number of multipliers, but also reduces the word length requirement for the coefficients of an IS-95 CDMA baseband filter. The VLSI implementation shows that the new structure reduces both the chip area and power consumption considerably compared with the direct-form implementation.

关键词： Attenuation Band pass filters Baseband Equalizers Finite impulse response filter IIR filters Multiaccess communication Passband Power filters Very large scale integration

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Flexible implementation of a WCDMA rake receiver 16

Flexible implementation of a WCDMA rake receiver

引用

ieee workshop on signal processing systems (sips 02)

作者： Harju, L Kuulusa, M Nurmi, J Tampere Univ Technol Inst Digital & Comp Syst FIN-33101 Tampere Finland

ISBN: (纸本)0780375874

This paper presents an ASIC implementation of a WCDMA Rake receiver. The implementation is based on a FlexRake architecture that shares resources between multipath components and uses parallelism for multiple code channels. This approach facilitates the multipath allocation and improves the receiver modularity. The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells. Synthesis for 0.35 mum technology resulted in 0.894 mm(2) area and 3.63 mW power consumption at 2.7 V.

关键词： Application specific integrated circuits Computer architecture Delay estimation Diversity reception Fading Fingers Gold Multiaccess communication Multipath channels RAKE receivers

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Obtaining an Optimal Set of Head-Related Transfer Functions with a Small Amount of Measurements

Obtaining an Optimal Set of Head-Related Transfer Functions ...

引用

ieee International workshop on signal processing systems (sips)

作者： Parviainen, Mikko Pertila, Pasi Tampere Univ Technol Lab Signal Proc Tampere Finland

ISBN: (纸本)9781538604465

This article presents a method to obtain personalized Head-Related Transfer Functions (HRTFs) for creating virtual soundscapes based on small amount of measurements. The best matching set of HRTFs are selected among the entries from publicly available databases. The proposed method is evaluated using a listening test where subjects assess the audio samples created using the best matching set of HRTFs against a randomly chosen set of HRTFs from the same location. The listening test indicates that subjects prefer the proposed method over random set of HRTFs.

关键词： acoustic signal processing acoustic measurements headphones

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Reduced Complexity FPGA implementation for UF-OFDM Frequency Domain Transmitter

Reduced Complexity FPGA Implementation for UF-OFDM Frequency...

引用

ieee International workshop on signal processing systems (sips)

作者： Medjkouh, Said Nadal, Jeremy Nour, Charbel Abdel Baghdadi, Amer Inst Mines Telecom IMT Atlantique Lab STICC CNRS Technopole Brest Iroise F-29238 Brest France

ISBN: (纸本)9781538604465

Universal Filtered Orthogonal Frequency Division Multiplexing (UF-OFDM) is considered one of the main waveform candidates to overcome the challenges facing the next generation of mobile communication systems. Due to its spectral properties it can support relaxed synchronization, low-latency communications and flexible time transmission interval. Nevertheless, the available recent literature addresses the potential of this waveform mainly from communication performance perspective, and sometimes presents a rough estimation of the complexity. Therefore, it becomes high of interest to seek efficient hardware implementations. In this paper, a reduced complexity pipelined architecture is proposed for UF-OFDM frequency domain transmitter. Using LTE parameters, the proposed UF-OFDM FDA architecture uses around 3.6 times less hardware ressources than the straightforward implementation.

关键词： UF-OFDM OFDM 5G FPGA

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Recursive filtering on SIMD architectures

Recursive filtering on SIMD architectures

引用

ieee workshop on signal processing systems

作者： Schaffer, R Hosemann, M Merker, R Fettweis, G Dresden Univ Technol Dept Elect Engn & Informat Technol D-8027 Dresden Germany

ISBN: (纸本)0780377958

Recursive filters are used frequently in digital signal processing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software solutions often are preferable for their speed of implementation and flexibility. However, contemporary DSPs are mostly not fast enough to perform filtering for high data-rates or large filters. A method to increase the computational power of a DSP without sacrificing efficiency is to use multiple processor elements controled by the single-instruction multiple-data (SIMD) paradigm. The parallelization of recursive algorithms is difficult, because of the data dependencies. We are using design methods for parallel procesor arrays to realize implementations that can be used on a parallel DSP. Further, we are focusing on the partitioning of the algorithm so that the realization can be used for different architectures. Consequences for the architecture are considered, too.

关键词： Computer architecture Digital filters Digital signal processing Digital signal processors Filtering Hardware IIR filters Partitioning algorithms Process control signal processing algorithms

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design Kernel Exploration Using QBF-Based Boolean Matching

Design Kernel Exploration Using QBF-Based Boolean Matching

引用

ieee International workshop on signal processing systems (sips)

作者： Preusser, Thomas B. Erxleben, Fredo Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781509033614

The synthesis and mapping of user designs to configurable hardware is typically performed by heuristics. These approaches analyze the decomposability of the combinational user functions as a starting point and derive appropriate mappings to LUT structures or pull them in from pre-computed implementation libraries. In everyday use, this generally achieves a very competitive trade-off between the time spent for the synthesis and the quality of the produced implementations. A higher pressure on the optimality of an implementation exists when implementation libraries are generated or when critical kernels that are extensively duplicated in a massively parallel design are implemented. In these cases, a formal statement that an implementation within fewer LUTs or a smaller combinational depth is strictly impossible is very valuable. We present a tool that formulates the task of mapping a user design to a configurable hardware structure as a quantified boolean formula (QBF). It then uses a QBF solver to either compute an implementing configuration or to know for sure that the desired functionality cannot be implemented within the provided hardware. In the context of this tool, we also describe different approaches to model configurable interconnects and present the impact of these modelling approaches on the time needed to solve the mapping tasks.

关键词： Mapping

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design AND implementation OF A HIGH DATA RATE MICS DIGITAL BASEBAND TRANSMITTER

DESIGN AND IMPLEMENTATION OF A HIGH DATA RATE MICS DIGITAL B...

引用

ieee workshop on signal processing systems (sips)

作者： Im, Junha Lee, Sangmin Kim, Jaeseok Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

ISBN: (纸本)9781457719219

An efficient design and VLSI implementation of a high data rate Medical Implant Communications Service (MICS) digital baseband transmitter for implantable medical devices is proposed in this paper. An orthogonal frequency division multiplexing (OFDM)-based multicarrier scheme is used to overcome the data rate limitation caused by the narrow bandwidth of 300 kHz. The proposed transmitter can support enhanced data rate by utilizing multiple channels simultaneously. Furthermore, to satisfy the MICS regulation, various schemes are applied including optimized subcarrier allocation for inverse fast Fourier transform (IFFT) and additional sidelobe suppression technique. The proposed transmitter with optimized hardware architecture is verified by VLSI implementation and it can support a maximum data rate of 4.86 Mbps, which is more than ten times faster than the previous systems.

关键词： VLSI medical implant communications service (MICS) digital baseband multicarrier orthogonal frequency division multiplexing (OFDM)

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An efficient implementation of hierarchical image coding

An efficient implementation of hierarchical image coding

引用

ieee workshop on signal processing systems

作者： Lee, J Vijaykrishnan, N Irwin, MJ Chandramouli, R Penn State Univ Microsyst Design Lab University Pk PA 16802 USA

ISBN: (纸本)0780377958

An efficient technique for hierarchical image coding is proposed, which divides an image into its multiple resolution versions with minimum hardware cost. Since the proposed technique uses discrete cosine transform (DCT) over each frequency band data, obtained directly from DCT domain by multiplying pre-calculated matrices, compatibility can be preserved easily with DCT-based image/video standards. First, we present the 1-D case, followed by an extension to the 2-D case. The proposed coder is observed to result in significant reduction of memory and computational complexity requirement with higher peak signal to noise ratio (PSNR), when compared with traditional hierarchical image coding method.

关键词： Discrete cosine transforms Frequency Image coding Image reconstruction Image resolution Nonlinear filters Scalability Video compression Video on demand Videoconference

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