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共 1150 条记录，以下是121-130 订阅

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Efficient direct 2D architecture for lifted biorthogonal DWT

Efficient direct 2D architecture for lifted biorthogonal DWT

引用

ieee workshop on signal processing systems

作者： Alam, M Badawy, W Dimitrov, V Jullien, G Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada

ISBN: (纸本)0780377958

This paper presents a new algorithm for 2D nonseparable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of filter of wavelet transform written as (LxM) tap 2D filter. The results are efficient architectures for real time signal processing, which don't require transpose memory for 2D processing of data. The proposed architecture exploits in place implementation inherit from the algorithm and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in architecture is scheduled carefully by pipelining the lifted steps, which allows two or four times faster processing than the direct implementation. The architecture therefore allows lowering the clock frequency by two/four. The proposed architecture operates at high speed/consumes low power and has reduced computational complexity as compared to already published filter and lifted based bi-orthogonal wavelet architectures.

关键词： Biomedical signal processing Clocks Computer architecture Discrete wavelet transforms Filters Parallel processing Pipeline processing Processor scheduling signal processing algorithms Wavelet transforms

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An implementation of Turbo Equalization Using Cyclic Prefix in LTE Downlink System

An Implementation of Turbo Equalization Using Cyclic Prefix ...

引用

ieee International workshop on signal processing systems (sips)

作者： Chen, Yun Zhang, Qichen Hu, Yuanzhou Ding, Na Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781467396042

In this paper, an implementation of turbo equalization using cyclic prefix in LTE downlink system is proposed. In comparison with conventional equalization schemes, the using of cyclic prefix can enhance the SNR performance by about 1 dB in AWGN channel and more in multi-path channel with Doppler frequency influence [3]. In this paper, the turbo equalizer presented in [3] is extended to 16QAM and 64QAM to support LTE system. Furthermore turbo encoder and decoder, scrambler and interleaver are designed according to the demands of LTE standard. The simulation results show that the algorithms can achieve ideal performance enhancement in LTE system comparing to conventional schemes.

关键词： turbo equalization LTE soft information GMP

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Efficient IMDCT core designs for audio signal processing

Efficient IMDCT core designs for audio signal processing

引用

ieee workshop on signal processing systems

作者： Wu, PS Hwan, YT Natl Yunlin Univ Sci & Technol Dept Elect Engn Toulin 640 Yunlin Taiwan

ISBN: (纸本)0780377958

Filter bank processing techniques based on MDCT/IMDCT have been widely adopted in various audio codec standards. Most published IMDCT computing algorithms focus mainly on either the reduction of computing complexity but overlook the hardware realization issues, e.g. memory access complexity and the efficient mapping of computing kernel. In this paper, by exploiting the symmetric properties in computation, we first convert an N-point IMDCT to an N/2-point DCT-II problem. Fast DCT-II computing scheme is next derived and the overall scheme is further optimized to remove redundancy. Based on the proposed fast IMDCT computing scheme, a novel design mapping is developed to minimize memory access complexity without stalling the pipelined computation. The mapping features simple address generation, small temporary storage size and low access bandwidth. Performance analyses show that, given the same hardware resource allocation, the proposed design can outperform other well known IMDCT designs in terms of memory storage size, computing latency or fixed point implementation error.

关键词： Code standards Codecs Discrete cosine transforms Filter bank Hardware Kernel Redundancy signal design signal processing signal processing algorithms

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Scheduling and allocation of single-chip multiprocessors for multimedia

Scheduling and allocation of single-chip multiprocessors for...

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Li, YB Wolf, W Princeton Univ Princeton United States

ISBN: (纸本)0780338065

Software synthesis is an increasingly important problem in the design of digital signal processing systems, since multimedia systems in particular are increasingly implemented using a combination of programmable and hardwired processing elements, This paper describes new algorithms for system-level software synthesis, namely the scheduling and allocation of a set of tasks executing on a heterogeneous multiprocessor, The algorithm is hierarchical: it takes advantage of the hierarchical structure of the system's task graph to hierarchically allocate and schedule processes on the multiprocessor to meet the hard real-time constraints on the tasks. Our algorithm takes into account of both the on-chip and off-chip data communications and the behaviors of data cache memories. It can significantly improve task schedulability by carefully scheduling processes and data transfers to minimize data cache misses and off-chip data accesses.

关键词： Digital signal processing

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Automatic coarse-grain partitioning and automatic code generation for heterogeneous architectures

Automatic coarse-grain partitioning and automatic code gener...

引用

ieee workshop on signal processing systems

作者： Raulet, M Babel, M Déforges, O Nezan, JF Sorel, Y INSA Rennes CNRS UMR 6164 IETR F-35000 Rennes France

ISBN: (纸本)0780377958

Real time signal, image, and control applications have very important time constraints, involving the use of several powerful numerical calculation units. The aim of our project is to develop a fast and automatic prototyping process dedicated to parallel architectures made of both PC and several last generation Texas Instruments digital signal processors : TMS320C6X DSP. The process is based on SynDEx, a CAD software improving algorithm implementation onto multi-processor architectures by finding the best matching between an algorithm and an architecture. SynDEx kernels for automatic PC and DSP dedicated code generation have been developed with the new SynDEx functionalities. A full coding application (LAR) illustrates the results.

关键词： Application software Automatic control Digital signal processing Image coding Parallel architectures Prototypes signal processing algorithms Software algorithms Software prototyping Time factors

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A mixed QOS SDRAM controller for FPGA-based high-end image processing

A mixed QOS SDRAM controller for FPGA-based high-end image p...

引用

ieee workshop on signal processing systems

作者： Heithecker, S Lucas, AD Ernst, R Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Commun Network Engn D-3300 Braunschweig Germany

ISBN: (纸本)0780377958

High-end video and multimedia processing applications today require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, accessing SDRAM is a complex task, especially if multi-stream access, different stream types and realtime capability are an issue. This paper describes a multi-stream SDRAM controller IP that covers different stream types and applies memory scheduling to achieve high bandwidth utilization. Two different architectures are presented and discussed, simulation results with a realistic application configuration demonstrate up to 90% of maximum memory bandwidth utilization. The scheduler IP is suitable for FPGA implementation and is flexible enough to be used in other applications.

关键词： Bandwidth Communication system control Delay Digital signal processing Field programmable gate arrays HDTV Image processing Job shop scheduling Random access memory SDRAM

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Resource-Aware Optimization of Modular, Cascade Detection systems

Resource-Aware Optimization of Modular, Cascade Detection Sy...

引用

ieee International workshop on signal processing systems (sips)

作者： Le, Long N. Jones, Douglas L. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9781509033614

Detection systems in the emerging Internet of Things (IoT) paradigm, unlike existing stovepipe ones, are envisioned to be a platform for multiple applications. As a result, the design for IoT systems often places strong emphasis on modularity, where components can be composed to form various applications. This modular constraint creates new challenges in finding the optimal trade-off between resource consumption and performance of detection systems. This work focuses on the problem of optimizing modular detection systems whose modules are cascade. The solution results in a dynamic-programming-based algorithm that can optimize cascade detection systems with an arbitrary number of modules. Simulation results on both synthetic and real data confirm the superiority of an optimized system against unoptimized ones.

关键词： cascade detection system modular design resource-aware dynamic programming IoT

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DVFS Based Power Management for LDPC Decoders with Early Termination

DVFS Based Power Management for LDPC Decoders with Early Ter...

引用

ieee International workshop on signal processing systems (sips)

作者： Ghanaatian, Reza Burg, Andreas Ecole Polytech Fed Lausanne Telecommun Circuits Lab Lausanne Switzerland

ISBN: (纸本)9781538604465

Low-density parity check (LDPC) codes are a mature coding scheme in telecommunications and the low power implementation of corresponding decoders is an issue of significant importance for receivers with stringent power budgets. This paper presents a power reduction technique for LDPC decoders that further extends their energy-proportional behavior, obtained with early-termination (ET), by predicting the required number of iterations and by applying dynamic voltage and frequency scaling (DVFS). The number of expected iterations and the associated voltage/frequency settings are predicted with a novel algorithm that is based on the offline statistical analysis of the number of decoding iterations. This algorithm systematically trades the error-correcting performance up to a predefined approximation level for the achieved amount of power reduction beyond ET. Simulation and postlayout implementation results in a 28nm FD-SOI technology prove that the proposed algorithm, when integrated with an LDPC decoder, can significantly reduce the power consumption with negligible overhead.

关键词： Decoding Iterative decoding signal to noise ratio Prediction algorithms Energy consumption Approximation algorithms

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Task concurrency analysis and exploration of visual texture decoder on a heterogeneous platform

Task concurrency analysis and exploration of visual texture ...

引用

ieee workshop on signal processing systems

作者： Ma, Z Wong, C Delfose, E Vounckx, J Catthoor, F Himpe, S Deconinck, G Leuven, KU IMEC DESICS Div Louvain Belgium

ISBN: (纸本)0780377958

The emerging of mobile multimedia terminals has given rise to growing demands for the power-efficient and scalable image transmission. Visual Texture Coding (VTC) has attracted increasing attention due to its scalability when transmitting still images. Nowadays, the implementation of such VTC decoders has not yet considered the need of energy performance trade-offs at the system-level. We have applied systematic system-level design techniques to analyze the VTC decoder and explore its timing-energy trade-off space by using our concurrent task scheduling exploration techniques. The approach presented in this paper allows a system designer to select the optimal heterogeneous platform configuration for a given speed of the VTC decoder while minimizing the global energy consumption.

关键词： Concurrent computing Decoding design optimization Discrete wavelet transforms Energy consumption Image coding Multimedia systems Scalability Scheduling Wavelet coefficients

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Systolic interpolation architectures for soft-decoding Reed-Solomon codes

Systolic interpolation architectures for soft-decoding Reed-...

引用

ieee workshop on signal processing systems

作者： Ahmed, A Shanbhag, NR Koetter, R Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)0780377958

We present a systolic algorithm for performing interpolation, a computationally intensive kernel found in algebraic soft-decoding of Reed-Solomon codes. We reformulate the interpolation algorithm, resulting in the systolic interpolation algorithm, which can compute a reduced number of candidate polynomial coefficients. Using the dependence graph of the algorithm, we realize a low-latency interpolation architecture and a high-throughput interpolation architecture. These architectures are compared against previously proposed architectures for a RS soft-decoder. We derive expressions for the latency of the systolic implementations and show that, for a reasonable hardware constraint, the low-latency systolic implementation reduces latency by 34% for a [255, 239] RS code. For the same code and hardware constraints, the high-throughput implementation with a block pipelining depth of 5, increases throughput by 68%. In addition, the critical path of both the low-latency and the high-throughput implementation is smaller than that of previously proposed architectures.

关键词： Computer architecture Delay Hardware Interpolation Iterative decoding Kernel Pipeline processing Polynomials Reed-Solomon codes Throughput

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